SH target - disable @(r0,rm) addressing mode?

[tm_gccmail@mail.kloo.net]

On Wed, 5 Feb 2003, Joern Rennecke wrote:

> tm_gccmail@mail.kloo.net wrote:
> > The generalized @(rm,rn) approach seems better than faking a 3AC add
> > because there's only one extra instruction generated versus two.
> 
> No, in the example assembler code you posted, most of the r0 values
> were calculated with an add at the end.  By allowing a 3-address add,
> register allocation would be less inclined to do the entire calculation
> in r0; with the two-address add replaced by a three-address add, we'll
> end up with one extra instruction, a register-register move in front
> of the add, which can be issued in the same cycle as the add itself.

I don't think this allows the scheduler to move the loads, though?

The primary problem (as I see it) is the dependency of each load on the r0
register, which limits the scheduling freedom.

Maybe reenabling the first instruction scheduling pass is a cleaner
solution?


Toshi