machine description porting question.

[Spundun Bhatt]

Hi,
I am porting gcc to a new platform and it seems this mailing list is the 
closest match. My apologies if this is not the correct place.
The machine that I am porting to has an instruction set similar to IBM 
rs6000, so we have taken rs6000 config files as the tmplate and are 
trying to make modifications to it.
My question is mainly regarding adding a temporary register in any insn 
definition in the machine description file.
the scenario:
my machine doesnt have a compare instruction so I want to use subc 
instruction (subtract and modify cc).
The compare instruction on powerpc looks similar to cmp RA,RB while 
subtract instruction on my architecture looks like SUBC rD,rA,rB.
So gcc has to allocate a temporary register for rD, and I dont know how 
to go about that. I have tried to look at the docs and "using and 
porting gnu cc" a lot but still cant get a hang of it.
I have tried two different tricks with no luck, they are described 
below. I would appreciate your comments on it.
The original insn in gcc-2.95.2 's md file looks like this:
(define_insn ""
  [(set (match_operand:CC 0 "cc_reg_operand" "=y")
    (compare:CC (match_operand:SI 1 "gpc_reg_operand" "r")
            (match_operand:SI 2 "reg_or_short_operand" "rI")))]
  ""
  "{cmp%I2|cmpw%I2} %0,%1,%2"
  [(set_attr "type" "compare")])

My 1'st try:
Looking at the documentation and the md file, the clobber template 
looked suitable here. And I tried the following but the instruction that 
matched the previous pattern refused to match this new template and gcc 
aborted (saying no match found for insn).
(define_insn ""
  [(set (match_operand:CC 0 "cc_reg_operand" "=y,y")
    (compare:CC (match_operand:SI 1 "gpc_reg_operand" "r,r")
            (match_operand:SI 2 "reg_or_short_operand" "r,I")))
   (clobber (match_scratch:SI 3 "=r,r"))
  ]
  ""
  "@
   SUBC R%3,R%1,R%2
   ADDIC R%3,R%1,%n2"
  [(set_attr "type" "compare")])

My 2'd try:
Again the documentation said that if the template matches, the compiler 
tries to do tweaks to make the constraints match. so I thought
cmp R1,R2 could be replaced by mr (move register) R3,R1 followed by SUBC 
R3, R3, R2, and here the need for extra operand should be eliminated 
hoping that the first instruction(move) will be generated by compiler to 
match the constraint... so I give a '+' in the constraint of op1 to make 
it writable... indicating to the compiler that its going to be written. 
This time the compiler matched the insn (which should make you all trust 
all the other changes that I have made) but doesnt generate any move 
instruction to back up the register ( I actually came up with a test 
case in c whose assembly output with -S switch was wrong due to this).

(define_insn ""
  [(set (match_operand:CC 0 "cc_reg_operand" "=y,y")
    (compare:CC (match_operand:SI 1 "gpc_reg_operand" "+r,r")
            (match_operand:SI 2 "reg_or_short_operand" "r,I")))
  ]
  ""
  "@
   SUBC R%1,R%1,R%2
   ADDIC R%1,R%1,%n2"
  [(set_attr "type" "compare")])

I know that I dont understand a lot of things, but can anyone please 
point out over here my mistakes?
Thanx a lot
Spundun