BBRO on non-pipelined processors - bad?

[tm]

I'm looking at BBRO and how it relates to the Hitachi H8/300 series.

Simply speaking, I can't see a reason why it should be enabled for the
H8/300:

1) The H8/300 has a constant-cycle conditional branch, e.g. it takes the
same number of clocks regardless of whether it's taken or not taken, and

2) The H8/300 has no cache, so there aren't any "minimization of cache
line fill" advantages.

Given these two factors, can we disable BBRO for the H8/300 series?
It adds significantly to code size.

I'd like to create a target macro defined something like:

#define CONSTANT_CYCLE_BRANCH 1

...and then we can do in toplev.c:

#ifdef CACHE_LOG
	if (!CONSTANT_CYCLE_BRANCH || CACHE_LOG)) {
		(call bbro here)
	}
#endif

Is this acceptable?

Toshi