two dfa problems

[Vladimir N. Makarov]

Richard Henderson wrote:

> Both of these issues show up with -mcpu=ev5, with the patch attached,
> on the fortran test case also attached.
>
> (1) Exponential behaviour in max_issue.
>
>     While compiling (iirc) iqtest_, we have 18 instructions ready at
>     the beginning of the block, which as far as I can see causes us
>     to try 2**18 alternatives.  Certainly the compiler hangs for
>     longer than I cared to wait.
>
>     I think the algorithm here is wrong, but I don't know how to fix
>     it exactly.  The hack attached prevents the exponential runaway,
>     but I think we should not be trying alternatives with instructions
>     of the same type.  That is, once we've tried an instruction of
>     type TYPE_IADD at position 0, we should not try a different insn
>     of type TYPE_IADD there, since it won't help produce a better
>     sloting.
>
> (2) Too many instructions issued per cycle.
>
>     The .28.sched2 dump contains for MAIN__
>
>          16--> 1144 $29=unspec[$29,0x3e] 10            :ev5_e01
>          16--> 34   $16=$9                             :ev5_e01
>          16--> 38   $18=0x18                           :ev5_e01
>          16--> 40   $19=0x18                           :ev5_e01
>
>     which has overcommitted both E0 and E1.  The issue rate is
>     set to 4 because we can issue to E0,E1,FA,FM in one cycle,
>     but that is not the case here.  I'm not sure what is going on.

Richard, Thanks for the information.

I've found that a wrong automata is generated.  I'll look at it.  May be the
problem is in 64bit host.  As I know it was not tested on 64bit host.

Vlad