Access size problem on ARM architecture

[Richard Earnshaw]

> >No warnings or errors are displayed.
> >The generated assembly file contains:
> >
> >        ldr    r3, [r2, #24]!  @ loadhi
> >
> >which is wrong since r3 is loaded with a 32 bit value instead of 16 bit.
> >This leads to wrong behaviour of the while statement.
> 
> You should find that this instruction is followed by:
> 
> 	mov	r3, r3, lsl #16
> 	cmp	r0, e3, lsr #16
> 
> or some similar construct that drops the unwanted bits from the register.
> If you are seeing genuinely wrong behaviour, please post a complete testcase 
> that exhibits the problem.
> 

Phil,

We already have one: PR-2623.  I don't have time to look into it at the 
moment, but the solution is to split the loadhi_preinc and loadhi_predec 
patterns into armv4 and non-armv4 variants, remembering that the offsets 
for ldrh are more limited than for ldr.

Similar fixes may also be needed for the post-inc peepholes.

R.