Branch breakage on IRIX 6.5

[Mark Mitchell]

>>>>> "Richard" == Richard Henderson <rth@redhat.com> writes:

    Richard> If this is somewhat predictable (e.g. always slot 0 in
    Richard> the register save area) see the Alpha version for
    Richard> inspiration.  Otherwise, see rs6000.md, eh_set_lr_si +
    Richard> splitter, which delays the memory store until after
    Richard> reload, when the stack offset is known.

OK, I see.

This is a little more than I want to tackle right now.

Gavin, as the MIPS maintainer would you like to make a go at this?  It
would be very useful, since otherwise we will have a significant
regression for MIPS in GCC 3.0.

Thanks,

--
Mark Mitchell                   mark@codesourcery.com
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