c/859: sparc-specific pessimal code for simple loop

[Richard Henderson]

On Tue, Nov 21, 2000 at 09:35:59PM -0000, jbuck@synopsys.com wrote:
> .LL6:
>         sll     %i2, 3, %i0
>         ldd     [%i3+%i0], %f6
>         add     %i2, 1, %i2
>         fmovs   %f6, %f2
>         cmp     %i2, %i1
>         fmovs   %f7, %f3
>         bl      .LL6
>         faddd   %f4, %f2, %f4
[...]
> void check(double);
> void test0(double* first, double* last)
> {
>   int n, pdiff = last - first;
>   double result = 0;
>   for (n = 0; n < pdiff; ++n) result += first[n];
>   check(result);
> }

Guys, what is the purpose of the 'T' EXTRA_CONSTRAINT?  As far
as I can tell all it's doing is confusing reload.

This is a STRICT_ALIGNMENT machine, therefore DFmode and DImode
operands must be 8-byte aligned, thus the EXTRA_CONSTRAINT check
ought to be redundant, no?

As it is, reload winds up choosing the e/e alternative (no telling
how it intends to make progress that way) and pushing the entire
mem as a reload.  I didn't check what alternative matches after
reload, but Clearly things are confused.

However, if I replace 'T' with 'm' as follows, I don't get the
extra DFmode copy.

Joe, as for the lack of strength-reduction here, this is something
that I've mentioned before to Bernd.  It is fallout from some code
he wrote a while back to improve the overly aggressive GIV reduction
problem on SMALL_REGISTER_CLASS machines.  In response he outlined
some thoughts on how to better to choose groups of GIVs to reduce.
At the moment I don't recall what state that patch was in...


r~



Index: sparc.md
===================================================================
RCS file: /cvs/gcc/egcs/gcc/config/sparc/sparc.md,v
retrieving revision 1.115
diff -c -p -d -r1.115 sparc.md
*** sparc.md	2000/11/14 18:05:45	1.115
--- sparc.md	2000/11/22 06:37:06
***************
*** 3281,3288 ****
  
  ;; Be careful, fmovd does not exist when !v9.
  (define_insn "*movdf_insn_sp32"
!   [(set (match_operand:DF 0 "nonimmediate_operand" "=e,T,U,T,o,e,*r,o,e,o")
! 	(match_operand:DF 1 "input_operand"    "T#F,e,T,U,G,e,*rFo,*r,o#F,e"))]
    "TARGET_FPU
     && ! TARGET_V9
     && (register_operand (operands[0], DFmode)
--- 3281,3288 ----
  
  ;; Be careful, fmovd does not exist when !v9.
  (define_insn "*movdf_insn_sp32"
!   [(set (match_operand:DF 0 "nonimmediate_operand" "= e,m,U,m,o,e,  *r, o")
! 	(match_operand:DF 1 "input_operand"        "m#F,e,m,U,G,e,*rFo,*r"))]
    "TARGET_FPU
     && ! TARGET_V9
     && (register_operand (operands[0], DFmode)
***************
*** 3296,3306 ****
    #
    #
    #
-   #
-   #
    #"
!  [(set_attr "type" "fpload,fpstore,load,store,*,*,*,*,*,*")
!   (set_attr "length" "1,1,1,1,2,2,2,2,2,2")])
  
  (define_insn "*movdf_no_e_insn_sp32"
    [(set (match_operand:DF 0 "nonimmediate_operand" "=U,T,o,r,o")
--- 3296,3304 ----
    #
    #
    #
    #"
!  [(set_attr "type" "fpload,fpstore,load,store,*,*,*,*")
!   (set_attr "length" "1,1,1,1,2,2,2,2")])
  
  (define_insn "*movdf_no_e_insn_sp32"
    [(set (match_operand:DF 0 "nonimmediate_operand" "=U,T,o,r,o")