BOOTSTRAP FAILURE: segementation fault in genattrtab under hpux
John David Anglin
dave@hiauly1.hia.nrc.ca
Wed Nov 15 15:09:00 GMT 2000
>
>
> In message < 200011152210.RAA23951@hiauly1.hia.nrc.ca >you write:
> > > 0xb8af8 <layout_type+64>: extrw,u r22,7,8,r3
> > > 0xb8afc <layout_type+68>: ldo 4c8(r9),r20
> > > 0xb8b00 <layout_type+72>: ldb r20(sr0,r3),rp
> > > 0xb8b04 <layout_type+76>: extrw,s rp,31,8,r19
> > > 0xb8b08 <layout_type+80>: cmpb,<> r25,r19,0xb9968 <layout_type+3760
> > >
> > >
> > > (gdb) stepi
> > > 0xb8b00 1235 if (TYPE_SIZE (type))
> > > (gdb) info reg r22 r3 r9 r20
> > > r22 7000000
> > > r3 7b03abb0
> > > r9 400050d8
> > > r20 400055a0
> > > (gdb) stepi
> >
> > The problem is the base and index registers in the ldb instruction
> > have been interchanged by rename registers. These are not interchangeable
> > on the pa because the space register for the instruction is loaded from
> > the base register. Richard and Jeff, any thoughts on how to fix this
> > one?
> Hmmm, presumably the insn was recognized because reload was completed and
> we didn't expect anyone to be mucking around with this stuff again, but
> regrename mucked things?
I think the reversal occurs because r3 is being used as an index register.
There is stuff in the machine definition like this:
(define_insn ""
[(set (match_operand:SI 0 "register_operand" "=r")
(zero_extend:SI (mem:HI
(plus:SI
(match_operand:SI 1 "basereg_operand" "r")
(match_operand:SI 2 "register_operand" "r")))))]
"! TARGET_DISABLE_INDEXING"
"*
{
/* Reload can create backwards (relative to cse) unscaled index
address modes when eliminating registers and possibly for
pseudos that don't get hard registers. Deal with it. */
if (operands[2] == hard_frame_pointer_rtx
|| operands[2] == stack_pointer_rtx)
return \"{ldhx|ldh} %1(%2),%0\";
else
return \"{ldhx|ldh} %2(%1),%0\";
}"
[(set_attr "type" "load")
(set_attr "length" "4")])
Dave
--
J. David Anglin dave.anglin@nrc.ca
National Research Council of Canada (613) 990-0752 (FAX: 952-6605)
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