ARM code generation bug with -O2...

[Richard Earnshaw]

> Hi Guys,
> 
> : This is a bug in the arm-specific peepholes (due to the fact that I hadn't 
> : read that bit of the ARM-ARM!).  If you search arm.md for define_peephole, 
> : you will find a set of post-inc peepholes.  The load variants already 
> : check that write-back doesn't occur to the base register (these aren't 
> : post-inc expressions).  The store variants need to check similarly (the 
> : test is very similar to the load ones).
> : 
> : Sorry, I don't have time to fix this right now, but with the above 
> : information you can probably have a go yourself.
> 
> Here is a patch to fix this problem.  If Richard approves it, I will
> check it in.

This is OK, but incomplete.  The tests should be the same as for post-inc 
ldr.  That is, that the base isn't being loaded/stored and that if the 
increment is a register, it isn't the same register as the base.  See the 
ldr peepholes in the same section for a template.

> 
> I will also generate a new test case and submit that for approval
> (seperately).
> 
> Cheers
> 	Nick
> 
> 2000-06-29  Nick Clifton  <nickc@cygnus.com>
> 
> 	* config/arm/arm.md: Fix store+post increment peepholes so
> 	that they do not attempt to overwrite the register being
> 	stored.
> 
> Index: gcc/config/arm/arm.md
> ===================================================================
> RCS file: /cvs/gcc/egcs/gcc/config/arm/arm.md,v
> retrieving revision 1.51
> diff -p -r1.51 arm.md
> *** arm.md	2000/06/03 10:44:59	1.51
> --- arm.md	2000/06/29 18:07:55
> ***************
> *** 7709,7715 ****
>   	(match_operand:QI 2 "s_register_operand" "r"))
>      (set (match_dup 0)
>   	(plus:SI (match_dup 0) (match_operand:SI 1 "index_operand" "rJ")))]
> !   "TARGET_ARM"
>     "str%?b\\t%2, [%0], %1")
>   
>   (define_peephole
> --- 7709,7715 ----
>   	(match_operand:QI 2 "s_register_operand" "r"))
>      (set (match_dup 0)
>   	(plus:SI (match_dup 0) (match_operand:SI 1 "index_operand" "rJ")))]
> !   "TARGET_ARM && (REGNO (operands[2]) != REGNO (operands[0]))"
>     "str%?b\\t%2, [%0], %1")
>   
>   (define_peephole
> ***************
> *** 7727,7733 ****
>   	(match_operand:SI 2 "s_register_operand" "r"))
>      (set (match_dup 0)
>   	(plus:SI (match_dup 0) (match_operand:SI 1 "index_operand" "rJ")))]
> !   "TARGET_ARM"
>     "str%?\\t%2, [%0], %1")
>   
>   (define_peephole
> --- 7727,7733 ----
>   	(match_operand:SI 2 "s_register_operand" "r"))
>      (set (match_dup 0)
>   	(plus:SI (match_dup 0) (match_operand:SI 1 "index_operand" "rJ")))]
> !   "TARGET_ARM && (REGNO (operands[2]) != REGNO (operands[0]))"
>     "str%?\\t%2, [%0], %1")
>   
>   (define_peephole