ARM code generation bug with -O2...

[Richard Earnshaw]

This is a bug in the arm-specific peepholes (due to the fact that I hadn't 
read that bit of the ARM-ARM!).  If you search arm.md for define_peephole, 
you will find a set of post-inc peepholes.  The load variants already 
check that write-back doesn't occur to the base register (these aren't 
post-inc expressions).  The store variants need to check similarly (the 
test is very similar to the load ones).

Sorry, I don't have time to fix this right now, but with the above 
information you can probably have a go yourself.


Here's another (probably even simpler) test case.


struct a{
  struct a *x;
}

foo(struct a *b)
{
  int i;

  for(i = 0; i < 1000; i++)
  {
    b->x = b;
    b++;
  }
}

R.

> Hi guys, 
> 
> The following code is distilled from nfscache.c in the Linux kernel. 
> 
> struct A {
> };
> 
> struct B {
>         struct A *next;
>         struct A *prev;
> };
> 
> static struct B         list[64];
> 
> void
> foo (void)
> {
>         struct B        *rh;
>         int             i;
> 
>         for (i = 0, rh = list; i < 64 ; i++, rh++)
>                 rh->next = rh->prev = (struct A *) rh;
> }
> 
> Building it with either gcc 2.95.2 or gcc 2.96 yields the following
> assembler warnings:
> 
> scott.s: Assembler messages:
> scott.s:18: Warning: source register same as write-back base
> 
> The assembler is complaining about the following assembler code generated
> by the compiler.
> 
> str     r3, [r3], #8
> 
> According to the ARM Architecture Reference I have this is an store operation
> using the immediate post-indexed addressing mode.
> 
> str     Rd, [Rn], #offset
> 
> In this particular case Rn == Rd.  One of the notes for store word (#3) states
> that if using pre or post indexed addressing mode, the results of the
> operation are UNPREDICTABLE if Rn == Rd.
> 
> Should the compiler be generating this assembler construct?  If it shouldn't
> it is beyond my capabilities to fix ATM.   The assembler output is attached
> as well.
> 
> @ Generated by gcc 2.95.2 20000212 (release) [Rebel.com] for ARM/elf
>         .file   "scott.c"
> gcc2_compiled.:
> .text
>         .align  2
>         .global foo
>         .type    foo,function
> foo:
>         @ args = 0, pretend = 0, frame = 0
>         @ frame_needed = 1, current_function_anonymous_args = 0
>         mov     ip, sp
>         stmfd   sp!, {fp, ip, lr, pc}
>         sub     fp, ip, #4
>         mov     r2, #63
>         ldr     r3, .L8
> .L6:
>         str     r3, [r3, #4]
>         str     r3, [r3], #8
>         subs    r2, r2, #1
>         bpl     .L6
>         ldmea   fp, {fp, sp, pc}
> .L9:
>         .align  2
> .L8:
>         .word   list
> .Lfe1:
>         .size    foo,.Lfe1-foo
> .bss
>         .align  2
> list:
>         .space  512
>         .ident  "GCC: (GNU) 2.95.2 20000212 (release) [Rebel.com]"
> 
> Scott
> 
> -- 
> Scott Bambrough - Software Engineer
> REBEL.COM    http://www.rebel.com
> NetWinder    http://www.netwinder.org