new g77 x86 ICE in 19990328

[Jeffrey A Law]

  In message < 37077BED.1A3C3A2C@moene.indiv.nluug.nl >you write:
  > > A hint, OP is the last register in the FP stack register class on the x86
  > 
  > Yeah, that gives it away, if paired with your earlier mail about the use
  > of the %argp register (which doesn't exist on the i386).
Yea.  The two hints together make it a lot easier :-)

We actually consider %argp a fake hard register (it makes certain aspects of
code generation easier).  However, it should always be eliminated in favor of
the frame or stack pointer by reload, so it should never appear in the rtl
stream after reload as completed.

  > Unfortunately, the latter does exist in the .../config/i386/i386.h list:
  > 
  > #define REG_ALLOC_ORDER \
  > /*ax,dx,cx,bx,si,di,bp,sp,st,st1,st2,st3,st4,st5,st6,st7,arg*/ \
  > {  0, 1, 2, 3, 4, 5, 6, 7, 8,  9, 10, 11, 12, 13, 14, 15, 16 }
  > 
  > So probably, i .EQ. 1.  Note that #define FIRST_PSEUDO_REGISTER 17.
Yup.  But can you see how this would cause a problem?

Consider cases where we want subword 1 of a hard register that is larger
than word mode.  That hunk of code assumes that all registers are exactly
one word wide, which is bogus.

Michael Hayes (privately) noted one of the bugs potential bugs in this code
REGNO (op) + i might not be a hard register due to the same problem.

I'll buy you both a beer at LinuxExpo :-)

  > Nice hole !   What's the solution you're proposing ?
Not sure yet. :-)  I want to ponder it a little since there's a variety of
issues related to the assumption that each hard register is exactly one word
wide.



jeff