Various bugs on powerpc-unknown-linux-gnu
Geoffrey KEATING
geoffk@discus.anu.edu.au
Thu Sep 4 22:04:00 GMT 1997
These patches all apply to egcs 2.90.01, snapshot dated 970821, generated
by taking egcs-ss-970814.tar.gz and applying egcs-ss-970814-970821.diff.gz.
It was configured with
./configure --prefix=/usr --with-gnu-as --with-gnu-ld
and correctly guessed the host, build, and target system to be
powerpc-unknown-linux-gnu (I'm using a glibc snapshot which will
eventually become glibc 2.1). It was built with
make CFLAGS="-O2 -mtune=601 -mmultiple -mno-string" bootstrap
make CFLAGS="-O2 -mtune=601 -mmultiple -mno-string" gnucompare
and passed the comparison (both before and after the patches).
Test cases, etc., are interleaved with the patches. I think the
patches can be applied independently, but I have not tested this.
Fri Sep 5 14:45:23 1997 Geoffrey KEATING <geoffk@ozemail.com.au>
* config/rs6000/t-ppccomm: Use -msdata=none for crtstuff.
* config/rs6000/rs6000.md: Deal more carefully with MQ on
601 processors.
* config/rs6000/rs6000.c: Avoid creating a stack frame
under SYSV ABI if we only need to save LR.
* config/rs6000/rs6000.md: Handle case where pseudo
holding GOT address ends up on stack.
* config/rs6000/rs6000.c: Avoid creating a stack frame
under SYSV ABI if we only need to save LR.
* config/rs6000/rs6000.c: Fix bug with nested functions
and -fpic.
* config/rs6000/rs6000.md: Use @plt always when compiling
PIC code.
* config/rs6000/rs6000.c: Pass excess FP arguments on the
stack not in integer registers.
* config/rs6000/rs6000.c: Fix various profiling bugs.
* config/rs6000/rs6000.h: Push and pop registers correctly
under SYSV ABI.
* Fix crtbegin.o, etc.; otherwise, the heads/tails of the constructor
chains can end up in .sdata rather than in .ctor/.dtor , which is not
helpful.
--- config/rs6000/t-ppccomm~ Sat Aug 16 04:58:22 1997
+++ config/rs6000/t-ppccomm Thu Aug 21 00:00:47 1997
@@ -67,3 +67,7 @@
$(T)scrt0$(objext): scrt0.c
$(GCC_FOR_TARGET) $(GCC_CFLAGS) $(INCLUDES) $(MULTILIB_CFLAGS) -c scrt0.c -o $(T)scrt0$(objext)
+
+# It is important that crtbegin.o, etc., aren't surprised by stuff in .sdata.
+CRTSTUFF_T_CFLAGS = -msdata=none
+CRTSTUFF_T_CFLAGS_S = -fpic -msdata=none
* The following crashes gcc with `cc1 -O2 -mcpu=601':
int drand48_iterate (unsigned long long x)
{ return (x*x) & 0xffff; }
Also, according to my 601 databook the following clobber the MQ:
mulli, mullw, mulhw, mulhwu, divw, divwu.
--- config/rs6000/rs6000.md.old Mon Aug 25 19:55:33 1997
+++ config/rs6000/rs6000.md Mon Aug 25 20:23:37 1997
@@ -4058,7 +4058,7 @@
[(set (match_operand:DI 0 "gpc_reg_operand" "=&r")
(mult:DI (zero_extend:DI (match_operand:SI 1 "gpc_reg_operand" "%r"))
(zero_extend:DI (match_operand:SI 2 "gpc_reg_operand" "r"))))]
- "TARGET_POWERPC && ! TARGET_POWERPC64"
+ "TARGET_POWERPC && ! TARGET_POWERPC64 && ! TARGET_POWER"
"*
{
return (WORDS_BIG_ENDIAN)
@@ -4088,6 +4088,21 @@
operands[4] = operand_subword (operands[0], 1 - endian, 0, DImode);
}")
+(define_insn "*umulsidi3_mq"
+ [(set (match_operand:DI 0 "gpc_reg_operand" "=&r")
+ (mult:DI (zero_extend:DI (match_operand:SI 1 "gpc_reg_operand" "%r"))
+ (zero_extend:DI (match_operand:SI 2 "gpc_reg_operand" "r"))))
+ (clobber (match_scratch:SI 3 "=q"))]
+ "TARGET_POWERPC && TARGET_POWER && ! TARGET_POWERPC64"
+ "*
+{
+ return (WORDS_BIG_ENDIAN)
+ ? \"mulhwu %0,%1,%2\;mullw %L0,%1,%2\"
+ : \"mulhwu %L0,%1,%2\;mullw %0,%1,%2\";
+}"
+ [(set_attr "type" "imul")
+ (set_attr "length" "8")])
+
(define_expand "smulsi3_highpart"
[(set (match_operand:SI 0 "gpc_reg_operand" "")
(truncate:SI
@@ -4135,7 +4150,20 @@
(sign_extend:DI
(match_operand:SI 2 "gpc_reg_operand" "r")))
(const_int 32))))]
- "TARGET_POWERPC"
+ "TARGET_POWERPC && ! TARGET_POWER"
+ "mulhw %0,%1,%2"
+ [(set_attr "type" "imul")])
+
+(define_insn ""
+ [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
+ (truncate:SI
+ (lshiftrt:DI (mult:DI (sign_extend:DI
+ (match_operand:SI 1 "gpc_reg_operand" "%r"))
+ (sign_extend:DI
+ (match_operand:SI 2 "gpc_reg_operand" "r")))
+ (const_int 32))))
+ (clobber (match_scratch:SI 3 "=q"))]
+ "TARGET_POWERPC && TARGET_POWER"
"mulhw %0,%1,%2"
[(set_attr "type" "imul")])
@@ -4147,7 +4175,20 @@
(zero_extend:DI
(match_operand:SI 2 "gpc_reg_operand" "r")))
(const_int 32))))]
- "TARGET_POWERPC"
+ "TARGET_POWERPC && ! TARGET_POWER"
+ "mulhwu %0,%1,%2"
+ [(set_attr "type" "imul")])
+
+(define_insn "*umulsi3_highpart_mq"
+ [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
+ (truncate:SI
+ (lshiftrt:DI (mult:DI (zero_extend:DI
+ (match_operand:SI 1 "gpc_reg_operand" "%r"))
+ (zero_extend:DI
+ (match_operand:SI 2 "gpc_reg_operand" "r")))
+ (const_int 32))))
+ (clobber (match_scratch:SI 3 "=q"))]
+ "TARGET_POWERPC && TARGET_POWER"
"mulhwu %0,%1,%2"
[(set_attr "type" "imul")])
* GCC creates frames unnecessarily under SVR4 when the LR is used. The
correct test is whether a routine called by this routine needs to save
the LR; we assume all routines need to save the LR (rather than bothering
to check), so the only question is whether this routine makes any calls.
--- config/rs6000/rs6000.c.orig Mon Aug 25 21:38:54 1997
+++ config/rs6000/rs6000.c Mon Aug 25 21:39:43 1997
@@ -3168,7 +3168,8 @@
else if (abi == ABI_V4 || abi == ABI_NT || abi == ABI_SOLARIS)
info_ptr->push_p = (total_raw_size > info_ptr->fixed_size
- || info_ptr->lr_save_p);
+ || (abi == ABI_NT ? info_ptr->lr_save_p
+ : info_ptr->calls_p));
else
info_ptr->push_p = (frame_pointer_needed
* Sometimes, the register holding the address of the GOT ends up on the
stack (in a routine that doesn't access global data very often). So we need
to get it back. This happens in the following, compiled with
cc1 -fpic -O2:
begin 644 tocreg-mem.c.gz
M'XL("%(A!#0"`W1O8W)E9RUM96TN8P#M6DMOVT80/E/HCY@<:I&4A$JNVZ2F
MG9Y:($"!'G),#8*B2)DP30I\V$D5_??.S"[)Y<.V1%F&7<A!;')F=G?>^VFU
MV;>5M_!\".-H"4&4P;U[[21V9@TRR<FC-%A&WH*Y:?"OIS++8;8=^SYR-`U*
MIJ"G<HRFLJ0XB$&#@?<U\Y*(1WA)$L56;1(DQ:R3%^6W@_4`P/[T.5^MO`0N
M09_!Q07`%`P8XPK,"^-[E3=3>4ZXNG8JWJG*6P3+(*MX/ZN\KPWFF<I,5X[K
M5;Q?5-XJ(1M*WJ\J;YDXJ^N*]U[ES4,GNJEX'U2>&V5)6/%^JZV71ZZRWFQ:
MMQY=J##)-<C;6$4(;-N-HS2KPIY>QTG&83"11V&QYQ8.*2.49DGN4J3O'#L,
MTLS.G"50D"B38+E*1.CEN]]X-^,[+_$Q8+:3+/&_YU@*,_&6=NK<>9)!FE8+
M?9E=C?%M&>6N0K*:BI$JG*=`PBN>[\N'*TLHL8CS>>@AQZ]SY#JH`*^/R?>#
MDKWJFB#_MA:V/_UM__GIKS^`?F&2-\B5_%T<+)@<QNX-+:5(WCK)#>8R&=&F
MFG:$8;/J/%[2M--Y[A.'JW`5IQ8%N2FV+@3\T%FF5A47DV70Z0M[E256%]V+
M%IWTN9-Z3<9]$F3>(YR.-02C8Q&TJW,FHM?$T0E(YO"Q/-09<\>]R5<%JV,0
M3<;T+L>+A[3;]SA1$)7.]X/0HY8F7^?A#;5$>B_:(#[A0^IQ*!N59[MY@C49
MYK<\(^MHYU&>>HOJG471`9S_H.02*D,/'/R'TK-*2*4-VW9.50F@%VS3`"A%
M.&5-@%LGQ/E12G1YZO?XT"6)N2%%"XI-81_#@R-9#5P\CY9>1@.1,(:Z.@.D
M#8ATYZ>N$_FHR!C\.+EU4!0["J^`^\?*0+<`*$'BT.&/:'<B]&*@9#2J7,XF
MF=P/:5Y+[$<-61(F26P?^(X)4UL%^V^U4BE2QEWT25<D<LF6;EK$$6TTTVXN
M%V`0=0B0PJZ@MQGWP2*[[F(TVP*Z+>.-50;1F!I09J%)S%4G7ZJ'?'IB-60Y
MI#<!-EZY?2(5R:9.[L.-Z9(>I=]!3'1_C<4$.OKPW24,_YD.15S7(BIUL$(#
MXR+,Z%":SQ^-"D*`R8)$FN='G$9;#S1J`YK@Z.5F]X7RS@`=_Z&X`<85G(#>
MWA\-4*``OA@\'XAI\:=FZ<PJR)@961#EGB1L2BU87[V6%::A0PK&Y*/:G,DB
M5?-JG:8&TGF=INUHF48KR1[!.@%<8M@G,WPX.1$@CBAG+`RM,%>VTD0<!=]M
MZIMX68Y]@%)>':%X;%,$E_*T2"L0]8>Q5RD/!A5SZ4G3!?83IK-ZC[ERUPEK
M^LH'DW#;B!)]-(()##'1%7.Y7IO&N8]$8!'#NI"CKD7^5FO4$,T,OE-F:HK?
MP=(VA;&REA\LIEKB5=6TB(6):K983_EPIW3DV92=@H:/J>*X:91>2^^#S+VF
MHA?ZN;CSPS`:GFM0*JMD'_<'SJL3F'Z=3F><RB8JO.[N]]J#C4NS;=K3T)(X
MLFV,JK[6RCX+4'V,PEV18#;#(?[#O11:,ABU8A_%AQ.=G*BB521K0@.@=E&#
MT=0^2AS,'E<D$:Y?&0:I+&UA$HQ(#6K=L:^WE#$P404/=&(8F+"8A3_5B<(-
M;-F&7^@WFB>W+.S\PKM%)6!VP^_PA..4#R>*YV2IS_,@Q$9ANZ&#'T+];S9E
MF6[J[8&B"'#)#Z)X2MOQTPI<(%5;-\/1FF"_>/@/Q,-OQP-)6'?:1O-"S-^>
MMG[$0C]M&+ML&VMVFVN^=`(V#'X'>X6WUW#I,:WIL5&],NI#MRT-N$#E>.IW
M?5,7IZ7QCZC"#D`+OG\_D`7O#<H=SL@#V\!B-2-.:##N:E.CE3B'K=P].VD_
M;[_::I#]HT;#E90@M)N)&@#%@:V#(=SHM4?YS^1<%*Y1GJG7-OIJVP_/ZXC"
MA`Y_%P:]:+&R*Q_7^@3.JAI^PKRS-Y]2"AB"<PU!9>W#J_II@$S=#6]*:#V9
MT#0?V:'D#^,)/%6<S&P/I(H1NR,H9>2KA4YUZW;$3*4S7SE8>BB$NXW;#AX5
M8PZ`BUIFM/I3M?AV2*B/LEM#H![J[@%ZGJW8]D,[NWKT%>7Q-L"FK/B#;3\[
MIV1_*-/IEA:&*4T^%'BI?+H;:NE=7P?%*6\C0VK'-,<3F.,)S/$$YG@"<SR!
M.9[`'$]@CB<P_\\3F(ZOH_C;*!AH/;[N&PR>0$T]\-(>2.E-8*3]T-&;P46]
M]X!>6.B0*&B+=K0S\CDLYNFC\3XXY[4@G,-BFP-G]%9XY@6VG9?$,%NBE\/C
MEMZ(I7^I'1:EO)%$>129:!I?@YLCX<8JKC&EPW--J]VW6H-ZD^E9+OVM^2Z?
M+K]+TL5$.`M?)RMNGDTF4E-CK'5?RN);68H%PA[.%KHB"J,1FDOS6II6WIY$
MNG`"WR+6Y5W3<7FGU(13Q9/R2JIA6*47E-NIXKJJ(6:UFFOHQ6@2D:,XF&*E
MFKQ8^A).R_N<Y76YR41<TZ.OWRPE8(,B9)^'YT2N])*7J?79M#Y"WF#;#!I7
-(C>#_P"*8K$;OS,``$1<
`
end
--- config/rs6000/rs6000.md~ Wed Aug 27 19:12:09 1997
+++ config/rs6000/rs6000.md Thu Aug 28 00:22:03 1997
@@ -5107,6 +5107,18 @@
"{l|lwz} %0,%a1@got(%2)"
[(set_attr "type" "load")])
+;; Sometimes, though, the GOT `register' will be on the stack. Deal with
+;; this case specially (because the usual handling can't see through
+;; the 'unspec').
+(define_split
+ [(set (match_operand:SI 0 "register_operand" "=r")
+ (unspec [(match_operand:SI 1 "got_no_const_operand" "")
+ (match_operand:SI 2 "memory_operand" "m")] 8))]
+ ""
+ [(set (match_dup 0) (match_dup 2))
+ (set (match_dup 0) (unspec [(match_dup 1)(match_dup 0)] 8))]
+ "")
+
;; For SI, we special-case integers that can't be loaded in one insn. We
;; do the load 16-bits at a time. We could do this by loading from memory,
;; and this is even supposed to be faster, but it is simpler not to get
* PIC code breaks when nested functions are used; for instance, the following
compiled with 'cc1 -O2 -fpic -Wall'. (The -Wall gives a nice visible crash,
rather than quietly generating invalid code.)
extern void x1(int), x2(int);
extern int c1, c2;
void x3 (int p) {
static inline void i1 (void) { x1(c1); }
static inline void i2 (void) { i1(); }
if (p) i2();
x2(c2);
}
--- config/rs6000/rs6000.c~ Thu Aug 28 00:39:28 1997
+++ config/rs6000/rs6000.c Fri Aug 29 01:16:00 1997
@@ -2292,6 +2292,12 @@
free (machine);
p->machine = (struct machine_function *)0;
+
+ /* If the nested function used the GOT, pic_offset_table_rtx would
+ have been set to the hard register that the function was using as
+ a pointer into the GOT table. Reset it to NULL so that if this
+ function uses the GOT it will get GOT_TOC_REGNUM. */
+ pic_offset_table_rtx = NULL;
}
/* Do anything needed before RTL is emitted for each function. */
* Code compiled with -fPIC still has relocations relating to branch
instructions.
[You might think that this would not happen, because the branches are
position-independent. If the branch instruction pointed to another
procedure in the same dynamic object, this would be true. But there
is no guarantee that the procedure is in the same dynamic object now,
and even if it was the procedure (if externally visible) might be
overriden by the executable or some earlier dynamic object; so the
relocation has to stay. So point the branch at the PLT, and then only
the PLT entry needs to be relocated. The binutils will do the right
thing if it the target of the branch is not exported from the shared
object.]
--- config/rs6000/rs6000.md~ Sun Aug 31 14:45:51 1997
+++ config/rs6000/rs6000.md Sun Aug 31 14:52:39 1997
@@ -7504,7 +7504,7 @@
else if (INTVAL (operands[2]) & CALL_V4_CLEAR_FP_ARGS)
output_asm_insn (\"creqv 6,6,6\", operands);
- return (flag_pic == 1) ? \"bl %z0@plt\" : \"bl %z0\";
+ return flag_pic ? \"bl %z0@plt\" : \"bl %z0\";
}"
[(set_attr "type" "branch")
(set_attr "length" "4,8")])
@@ -7574,7 +7574,7 @@
else if (INTVAL (operands[3]) & CALL_V4_CLEAR_FP_ARGS)
output_asm_insn (\"creqv 6,6,6\", operands);
- return (flag_pic == 1) ? \"bl %z1@plt\" : \"bl %z1\";
+ return flag_pic ? \"bl %z1@plt\" : \"bl %z1\";
}"
[(set_attr "type" "branch")
(set_attr "length" "4,8")])
* FP arguments get passed on the stack under SVR4 if they don't get a
register, not in GPRs.
--- config/rs6000/rs6000.c~ Wed Sep 3 19:06:04 1997
+++ config/rs6000/rs6000.c Wed Sep 3 20:13:42 1997
@@ -1330,9 +1330,11 @@
const0_rtx)));
}
- /* Long longs won't be split between register and stack */
+ /* Long longs won't be split between register and stack;
+ FP arguments get passed on the stack if they didn't get a register. */
else if ((DEFAULT_ABI == ABI_V4 || DEFAULT_ABI == ABI_SOLARIS) &&
- align_words + RS6000_ARG_SIZE (mode, type, named) > GP_ARG_NUM_REG)
+ (align_words + RS6000_ARG_SIZE (mode, type, named) > GP_ARG_NUM_REG
+ || (GET_MODE_CLASS (mode) == MODE_FLOAT && TARGET_HARD_FLOAT)))
{
return NULL_RTX;
}
* The SVR4 ABI suggests that the _mcount argument goes in r0. Also, the
address computation for the argument was adding the address to r11 instead
of storing it in r11. See below for a test case.
--- config/rs6000/rs6000.c~ Wed Sep 3 22:08:08 1997
+++ config/rs6000/rs6000.c Thu Sep 4 16:49:00 1997
@@ -4419,7 +4419,7 @@
fprintf (file, "\tbl _GLOBAL_OFFSET_TABLE_@local-4\n");
fprintf (file, "\tmflr %s\n", reg_names[11]);
fprintf (file, "\t%s %s,", (TARGET_NEW_MNEMONICS) ? "lwz" : "l",
- reg_names[11]);
+ reg_names[0]);
assemble_name (file, buf);
fprintf (file, "@got(%s)\n", reg_names[11]);
}
@@ -4443,21 +4443,21 @@
#endif
else if (TARGET_NEW_MNEMONICS)
{
- fprintf (file, "\taddis %s,%s,", reg_names[11], reg_names[11]);
+ fprintf (file, "\tlis %s,", reg_names[11]);
assemble_name (file, buf);
fprintf (file, "@ha\n");
fprintf (file, "\tstw %s,4(%s)\n", reg_names[0], reg_names[1]);
- fprintf (file, "\taddi %s,%s,", reg_names[11], reg_names[11]);
+ fprintf (file, "\taddi %s,%s,", reg_names[0], reg_names[11]);
assemble_name (file, buf);
fputs ("@l\n", file);
}
else
{
- fprintf (file, "\tcau %s,%s,", reg_names[11], reg_names[11]);
+ fprintf (file, "\tcau %s,0,", reg_names[11]);
assemble_name (file, buf);
fprintf (file, "@ha\n");
fprintf (file, "\tst %s,4(%s)\n", reg_names[0], reg_names[1]);
- fprintf (file, "\tcal %s,", reg_names[11]);
+ fprintf (file, "\tcal %s,", reg_names[0]);
assemble_name (file, buf);
fprintf (file, "@l(%s)\n", reg_names[11]);
}
* For the SYSV ELF ABI, the stack must keep 16-byte alignment at all times,
and the stack pointer must only be decremented by a 'store-with-update'
instruction storing the stack pointer (the VM architecture is
allowed to check this to detect wild stores below the bottom of the
stack). For instance, in the following:
int x3 (int p) {
int i1 (void) { return p; }
p++;
return i1();
}
when compiled with 'gcc -pg -O2 -S', I get, in part:
.section ".text"
.align 2
.type i1.2,@function
i1.2:
.section ".data"
.align 2
.LP0:
.long 0
.section ".text"
stwu 11,-4(1)
mflr 0
addis 11,11,.LP0@ha
stw 0,4(1)
addi 11,11,.LP0@l
bl _mcount
lwz 11,0(1)
addic 1,1,4
.extern _savefpr_32_l
.extern _restfpr_32_l
stwu 1,-32(1)
stw 11,8(1)
lwz 3,0(11)
addi 1,1,32
blr
.Lfe1:
.size i1.2,.Lfe1-i1.2
here, the 'stwu' is clearly bogus, and incidentally will cause the back chain
to turn into garbage. This also displays the bug with profiling described
above. Oh, and I'm pretty sure that's supposed to be `stu', not `tstu'.
--- config/rs6000/rs6000.h~ Wed Sep 3 20:19:08 1997
+++ config/rs6000/rs6000.h Thu Sep 4 17:29:26 1997
@@ -2908,8 +2908,13 @@
#define ASM_OUTPUT_REG_PUSH(FILE,REGNO) \
do { \
extern char *reg_names[]; \
- asm_fprintf (FILE, "\{tstu|stwu} %s,-4(%s)\n", reg_names[REGNO], \
- reg_names[1]); \
+ if (DEFAULT_ABI == ABI_V4 || DEFAULT_ABI == ABI_SOLARIS) \
+ asm_fprintf (FILE, "\t{stu|stwu} %s,-16(%s)\n\t{st|stw} %s,8(%s)\n", \
+ reg_names[1], reg_names[1], reg_names[REGNO], \
+ reg_names[1]); \
+ else \
+ asm_fprintf (FILE, "\t{stu|stwu} %s,-4(%s)\n", reg_names[REGNO], \
+ reg_names[1]); \
} while (0)
/* This is how to output an insn to pop a register from the stack.
@@ -2918,9 +2923,14 @@
#define ASM_OUTPUT_REG_POP(FILE,REGNO) \
do { \
extern char *reg_names[]; \
- asm_fprintf (FILE, "\t{l|lwz} %s,0(%s)\n\t{ai|addic} %s,%s,4\n", \
- reg_names[REGNO], reg_names[1], reg_names[1], \
- reg_names[1]); \
+ if (DEFAULT_ABI == ABI_V4 || DEFAULT_ABI == ABI_SOLARIS) \
+ asm_fprintf (FILE, "\t{l|lwz} %s,8(%s)\n\t{ai|addic} %s,%s,16\n", \
+ reg_names[REGNO], reg_names[1], reg_names[1], \
+ reg_names[1]); \
+ else \
+ asm_fprintf (FILE, "\t{l|lwz} %s,0(%s)\n\t{ai|addic} %s,%s,4\n", \
+ reg_names[REGNO], reg_names[1], reg_names[1], \
+ reg_names[1]); \
} while (0)
/* This is how to output an element of a case-vector that is absolute.
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