Generate big-endian code.
Generate little-endian code. This is the default for ‘mips*el-*-*’ configurations.
Generate code that runs on arch, which can be the name of a generic MIPS ISA, or the name of a particular processor. The ISA names are: ‘mips1’, ‘mips2’, ‘mips3’, ‘mips4’, ‘mips32’, ‘mips32r2’, ‘mips32r3’, ‘mips32r5’, ‘mips32r6’, ‘mips64’, ‘mips64r2’, ‘mips64r3’, ‘mips64r5’ and ‘mips64r6’. The processor names are: ‘4kc’, ‘4km’, ‘4kp’, ‘4ksc’, ‘4kec’, ‘4kem’, ‘4kep’, ‘4ksd’, ‘5kc’, ‘5kf’, ‘20kc’, ‘24kc’, ‘24kf2_1’, ‘24kf1_1’, ‘24kec’, ‘24kef2_1’, ‘24kef1_1’, ‘34kc’, ‘34kf2_1’, ‘34kf1_1’, ‘34kn’, ‘74kc’, ‘74kf2_1’, ‘74kf1_1’, ‘74kf3_2’, ‘1004kc’, ‘1004kf2_1’, ‘1004kf1_1’, ‘i6400’, ‘i6500’, ‘interaptiv’, ‘loongson2e’, ‘loongson2f’, ‘loongson3a’, ‘gs464’, ‘gs464e’, ‘gs264e’, ‘m4k’, ‘m14k’, ‘m14kc’, ‘m14ke’, ‘m14kec’, ‘m5100’, ‘m5101’, ‘octeon’, ‘octeon+’, ‘octeon2’, ‘octeon3’, ‘orion’, ‘p5600’, ‘p6600’, ‘r2000’, ‘r3000’, ‘r3900’, ‘r4000’, ‘r4400’, ‘r4600’, ‘r4650’, ‘r4700’, ‘r5900’, ‘r6000’, ‘r8000’, ‘rm7000’, ‘rm9000’, ‘r10000’, ‘r12000’, ‘r14000’, ‘r16000’, ‘sb1’, ‘sr71000’, ‘vr4100’, ‘vr4111’, ‘vr4120’, ‘vr4130’, ‘vr4300’, ‘vr5000’, ‘vr5400’, ‘vr5500’, ‘xlr’ and ‘xlp’. The special value ‘from-abi’ selects the most compatible architecture for the selected ABI (that is, ‘mips1’ for 32-bit ABIs and ‘mips3’ for 64-bit ABIs).
The native Linux/GNU toolchain also supports the value ‘native’, which selects the best architecture option for the host processor. -march=native has no effect if GCC does not recognize the processor.
In processor names, a final ‘000’ can be abbreviated as ‘k’ (for example, -march=r2k). Prefixes are optional, and ‘vr’ may be written ‘r’.
Names of the form ‘nf2_1’ refer to processors with FPUs clocked at half the rate of the core, names of the form ‘nf1_1’ refer to processors with FPUs clocked at the same rate as the core, and names of the form ‘nf3_2’ refer to processors with FPUs clocked a ratio of 3:2 with respect to the core. For compatibility reasons, ‘nf’ is accepted as a synonym for ‘nf2_1’ while ‘nx’ and ‘bfx’ are accepted as synonyms for ‘nf1_1’.
GCC defines two macros based on the value of this option. The first
_MIPS_ARCH, which gives the name of target architecture, as
a string. The second has the form
where foo is the capitalized value of
For example, -march=r2000 sets
"r2000" and defines the macro
Note that the
_MIPS_ARCH macro uses the processor names given
above. In other words, it has the full prefix and does not
abbreviate ‘000’ as ‘k’. In the case of ‘from-abi’,
the macro names the resolved architecture (either
"mips3"). It names the default architecture when no
-march option is given.
Optimize for arch. Among other things, this option controls the way instructions are scheduled, and the perceived cost of arithmetic operations. The list of arch values is the same as for -march.
When this option is not used, GCC optimizes for the processor specified by -march. By using -march and -mtune together, it is possible to generate code that runs on a family of processors, but optimize the code for one particular member of that family.
-mtune defines the macros
_MIPS_TUNE_foo, which work in the same way as the
-march ones described above.
Equivalent to -march=mips1.
Equivalent to -march=mips2.
Equivalent to -march=mips3.
Equivalent to -march=mips4.
Equivalent to -march=mips32.
Equivalent to -march=mips32r3.
Equivalent to -march=mips32r5.
Equivalent to -march=mips32r6.
Equivalent to -march=mips64.
Equivalent to -march=mips64r2.
Equivalent to -march=mips64r3.
Equivalent to -march=mips64r5.
Equivalent to -march=mips64r6.
Generate (do not generate) MIPS16 code. If GCC is targeting a MIPS32 or MIPS64 architecture, it makes use of the MIPS16e ASE.
MIPS16 code generation can also be controlled on a per-function basis
by means of
See Declaring Attributes of Functions, for more information.
Use (do not use) the MIPS16e2 ASE. This option modifies the behavior of the -mips16 option such that it targets the MIPS16e2 ASE.
Generate MIPS16 code on alternating functions. This option is provided for regression testing of mixed MIPS16/non-MIPS16 code generation, and is not intended for ordinary use in compiling user code.
Require (do not require) that code using the standard (uncompressed) MIPS ISA be link-compatible with MIPS16 and microMIPS code, and vice versa.
For example, code using the standard ISA encoding cannot jump directly to MIPS16 or microMIPS code; it must either use a call or an indirect jump. -minterlink-compressed therefore disables direct jumps unless GCC knows that the target of the jump is not compressed.
Aliases of -minterlink-compressed and -mno-interlink-compressed. These options predate the microMIPS ASE and are retained for backwards compatibility.
Generate code for the given ABI.
Note that the EABI has a 32-bit and a 64-bit variant. GCC normally generates 64-bit code when you select a 64-bit architecture, but you can use -mgp32 to get 32-bit code instead.
For information about the O64 ABI, see https://gcc.gnu.org/projects/mipso64-abi.html.
GCC supports a variant of the o32 ABI in which floating-point registers
are 64 rather than 32 bits wide. You can select this combination with
-mabi=32 -mfp64. This ABI relies on the
mfhc1 instructions and is therefore only supported for
MIPS32R2, MIPS32R3 and MIPS32R5 processors.
The register assignments for arguments and return values remain the same, but each scalar value is passed in a single 64-bit register rather than a pair of 32-bit registers. For example, scalar floating-point values are returned in ‘$f0’ only, not a ‘$f0’/‘$f1’ pair. The set of call-saved registers also remains the same in that the even-numbered double-precision registers are saved.
Two additional variants of the o32 ABI are supported to enable
a transition from 32-bit to 64-bit registers. These are FPXX
(-mfpxx) and FP64A (-mfp64 -mno-odd-spreg).
The FPXX extension mandates that all code must execute correctly
when run using 32-bit or 64-bit registers. The code can be interlinked
with either FP32 or FP64, but not both.
The FP64A extension is similar to the FP64 extension but forbids the
use of odd-numbered single-precision registers. This can be used
in conjunction with the
FRE mode of FPUs in MIPS32R5
processors and allows both FP32 and FP64A code to interlink and
run in the same process without changing FPU modes.
Generate (do not generate) code that is suitable for SVR4-style dynamic objects. -mabicalls is the default for SVR4-based systems.
Generate (do not generate) code that is fully position-independent, and that can therefore be linked into shared libraries. This option only affects -mabicalls.
All -mabicalls code has traditionally been position-independent, regardless of options like -fPIC and -fpic. However, as an extension, the GNU toolchain allows executables to use absolute accesses for locally-binding symbols. It can also use shorter GP initialization sequences and generate direct calls to locally-defined functions. This mode is selected by -mno-shared.
-mno-shared depends on binutils 2.16 or higher and generates objects that can only be linked by the GNU linker. However, the option does not affect the ABI of the final executable; it only affects the ABI of relocatable objects. Using -mno-shared generally makes executables both smaller and quicker.
-mshared is the default.
Assume (do not assume) that the static and dynamic linkers support PLTs and copy relocations. This option only affects -mno-shared -mabicalls. For the n64 ABI, this option has no effect without -msym32.
You can make -mplt the default by configuring GCC with --with-mips-plt. The default is -mno-plt otherwise.
Lift (do not lift) the usual restrictions on the size of the global offset table.
GCC normally uses a single instruction to load values from the GOT. While this is relatively efficient, it only works if the GOT is smaller than about 64k. Anything larger causes the linker to report an error such as:
relocation truncated to fit: R_MIPS_GOT16 foobar
If this happens, you should recompile your code with -mxgot. This works with very large GOTs, although the code is also less efficient, since it takes three instructions to fetch the value of a global symbol.
Note that some linkers can create multiple GOTs. If you have such a linker, you should only need to use -mxgot when a single object file accesses more than 64k’s worth of GOT entries. Very few do.
These options have no effect unless GCC is generating position independent code.
Assume that general-purpose registers are 32 bits wide.
Assume that general-purpose registers are 64 bits wide.
Assume that floating-point registers are 32 bits wide.
Assume that floating-point registers are 64 bits wide.
Do not assume the width of floating-point registers.
Use floating-point coprocessor instructions.
Do not use floating-point coprocessor instructions. Implement floating-point calculations using library calls instead.
Equivalent to -msoft-float, but additionally asserts that the
program being compiled does not perform any floating-point operations.
This option is presently supported only by some bare-metal MIPS
configurations, where it may select a special set of libraries
that lack all floating-point support (including, for example, the
If code compiled with -mno-float accidentally contains
floating-point operations, it is likely to suffer a link-time
or run-time failure.
Assume that the floating-point coprocessor only supports single-precision operations.
Assume that the floating-point coprocessor supports double-precision operations. This is the default.
Enable the use of odd-numbered single-precision floating-point registers for the o32 ABI. This is the default for processors that are known to support these registers. When using the o32 FPXX ABI, -mno-odd-spreg is set by default.
These options control the treatment of the special not-a-number (NaN)
IEEE 754 floating-point data with the
neg.fmt machine instructions.
By default or when -mabs=legacy is used the legacy treatment is selected. In this case these instructions are considered arithmetic and avoided where correct operation is required and the input operand might be a NaN. A longer sequence of instructions that manipulate the sign bit of floating-point datum manually is used instead unless the -ffinite-math-only option has also been specified.
The -mabs=2008 option selects the IEEE 754-2008 treatment. In this case these instructions are considered non-arithmetic and therefore operating correctly in all cases, including in particular where the input operand is a NaN. These instructions are therefore always used for the respective operations.
These options control the encoding of the special not-a-number (NaN) IEEE 754 floating-point data.
The -mnan=legacy option selects the legacy encoding. In this case quiet NaNs (qNaNs) are denoted by the first bit of their trailing significand field being 0, whereas signaling NaNs (sNaNs) are denoted by the first bit of their trailing significand field being 1.
The -mnan=2008 option selects the IEEE 754-2008 encoding. In this case qNaNs are denoted by the first bit of their trailing significand field being 1, whereas sNaNs are denoted by the first bit of their trailing significand field being 0.
The default is -mnan=legacy unless GCC has been configured with --with-nan=2008.
Use (do not use) ‘ll’, ‘sc’, and ‘sync’ instructions to implement atomic memory built-in functions. When neither option is specified, GCC uses the instructions if the target architecture supports them.
-mllsc is useful if the runtime environment can emulate the instructions and -mno-llsc can be useful when compiling for nonstandard ISAs. You can make either option the default by configuring GCC with --with-llsc and --without-llsc respectively. --with-llsc is the default for some configurations; see the installation documentation for details.
Use (do not use) revision 1 of the MIPS DSP ASE.
See MIPS DSP Built-in Functions. This option defines the
__mips_dsp. It also defines
__mips_dsp_rev to 1.
Use (do not use) revision 2 of the MIPS DSP ASE.
See MIPS DSP Built-in Functions. This option defines the
It also defines
__mips_dsp_rev to 2.
Use (do not use) the MIPS SmartMIPS ASE.
Use (do not use) paired-single floating-point instructions. See MIPS Paired-Single Support. This option requires hardware floating-point support to be enabled.
Use (do not use) MIPS Digital Media Extension instructions. This option can only be used when generating 64-bit code and requires hardware floating-point support to be enabled.
Use (do not use) the MIPS-3D ASE. See MIPS-3D Built-in Functions. The option -mips3d implies -mpaired-single.
Generate (do not generate) microMIPS code.
MicroMIPS code generation can also be controlled on a per-function basis
by means of
See Declaring Attributes of Functions, for more information.
Use (do not use) MT Multithreading instructions.
Use (do not use) the MIPS MCU ASE instructions.
Use (do not use) the MIPS Enhanced Virtual Addressing instructions.
Use (do not use) the MIPS Virtualization (VZ) instructions.
Use (do not use) the MIPS eXtended Physical Address (XPA) instructions.
Use (do not use) the MIPS Cyclic Redundancy Check (CRC) instructions.
Use (do not use) the MIPS Global INValidate (GINV) instructions.
Use (do not use) the MIPS Loongson MultiMedia extensions Instructions (MMI).
Use (do not use) the MIPS Loongson EXTensions (EXT) instructions.
Use (do not use) the MIPS Loongson EXTensions r2 (EXT2) instructions.
long types to be 64 bits wide. See -mlong32 for
an explanation of the default and the way that the pointer size is
int, and pointer types to be 32 bits wide.
The default size of
longs and pointers depends on
the ABI. All the supported ABIs use 32-bit
ints. The n64 ABI
longs, as does the 64-bit EABI; the others use
longs. Pointers are the same size as
or the same size as integer registers, whichever is smaller.
Assume (do not assume) that all symbols have 32-bit values, regardless of the selected ABI. This option is useful in combination with -mabi=64 and -mno-abicalls because it allows GCC to generate shorter and faster references to symbolic addresses.
Put definitions of externally-visible data in a small data section if that data is no bigger than num bytes. GCC can then generate more efficient accesses to the data; see -mgpopt for details.
The default -G option depends on the configuration.
Extend (do not extend) the -G behavior to local data too, such as to static variables in C. -mlocal-sdata is the default for all configurations.
If the linker complains that an application is using too much small data, you might want to try rebuilding the less performance-critical parts with -mno-local-sdata. You might also want to build large libraries with -mno-local-sdata, so that the libraries leave more room for the main program.
Assume (do not assume) that externally-defined data is in a small data section if the size of that data is within the -G limit. -mextern-sdata is the default for all configurations.
If you compile a module Mod with -mextern-sdata -G
num -mgpopt, and Mod references a variable Var
that is no bigger than num bytes, you must make sure that Var
is placed in a small data section. If Var is defined by another
module, you must either compile that module with a high-enough
-G setting or attach a
section attribute to Var’s
definition. If Var is common, you must link the application
with a high-enough -G setting.
The easiest way of satisfying these restrictions is to compile and link every module with the same -G option. However, you may wish to build a library that supports several different small data limits. You can do this by compiling the library with the highest supported -G setting and additionally using -mno-extern-sdata to stop the library from making assumptions about externally-defined data.
Use (do not use) GP-relative accesses for symbols that are known to be in a small data section; see -G, -mlocal-sdata and -mextern-sdata. -mgpopt is the default for all configurations.
-mno-gpopt is useful for cases where the
might not hold the value of
_gp. For example, if the code is
part of a library that might be used in a boot monitor, programs that
call boot monitor routines pass an unknown value in
(In such situations, the boot monitor itself is usually compiled
-mno-gpopt implies -mno-local-sdata and -mno-extern-sdata.
Allocate variables to the read-only data section first if possible, then next in the small data section if possible, otherwise in data. This gives slightly slower code than the default, but reduces the amount of RAM required when executing, and thus may be preferred for some embedded systems.
const variables in the read-only data section.
This option is only meaningful in conjunction with -membedded-data.
Specify whether GCC may generate code that reads from executable sections. There are three possible settings:
Instructions may freely access executable sections. This is the default setting.
MIPS16 PC-relative load instructions can access executable sections, but other instructions must not do so. This option is useful on 4KSc and 4KSd processors when the code TLBs have the Read Inhibit bit set. It is also useful on processors that can be configured to have a dual instruction/data SRAM interface and that, like the M4K, automatically redirect PC-relative loads to the instruction RAM.
Instructions must not access executable sections. This option can be useful on targets that are configured to have a dual instruction/data SRAM interface but that (unlike the M4K) do not automatically redirect PC-relative loads to the instruction RAM.
Enable (disable) use of the
relocation operators. This option has been superseded by
-mexplicit-relocs but is retained for backwards compatibility.
Use (do not use) assembler relocation operators when dealing with symbolic addresses. The alternative, selected by -mno-explicit-relocs, is to use assembler macros instead.
-mexplicit-relocs is the default if GCC was configured to use an assembler that supports relocation operators.
Trap (do not trap) on integer division by zero.
The default is -mcheck-zero-division.
MIPS systems check for division by zero by generating either a
conditional trap or a break instruction. Using traps results in
smaller code, but is only supported on MIPS II and later. Also, some
versions of the Linux kernel have a bug that prevents trap from
generating the proper signal (
SIGFPE). Use -mdivide-traps to
allow conditional traps on architectures that support them and
-mdivide-breaks to force the use of breaks.
The default is usually -mdivide-traps, but this can be overridden at configure time using --with-divide=breaks. Divide-by-zero checks can be completely disabled using -mno-check-zero-division.
Enable (disable) an optimization that pairs consecutive load or store instructions to enable load/store bonding. This option is enabled by default but only takes effect when the selected architecture is known to support bonding.
Enable (disable) direct unaligned access for MIPS Release 6. MIPSr6 requires load/store unaligned-access support, by hardware or trap&emulate. So -mno-unaligned-access may be needed by kernel.
Force (do not force) the use of
memcpy for non-trivial block
moves. The default is -mno-memcpy, which allows GCC to inline
most constant-sized copies.
Disable (do not disable) use of the
jal instruction. Calling
jal is more efficient but requires the caller
and callee to be in the same 256 megabyte segment.
This option has no effect on abicalls code. The default is -mno-long-calls.
Enable (disable) use of the
instructions, as provided by the R4650 ISA.
Enable (disable) use of the
instructions. The default is -mimadd on architectures
msub except for the 74k
architecture where it was found to generate slower code.
Enable (disable) use of the floating-point multiply-accumulate instructions, when they are available. The default is -mfused-madd.
On the R8000 CPU when multiply-accumulate instructions are used, the intermediate product is calculated to infinite precision and is not subject to the FCSR Flush to Zero bit. This may be undesirable in some circumstances. On other processors the result is numerically identical to the equivalent computation using separate multiply, add, subtract and negate instructions.
Tell the MIPS assembler to not run its preprocessor over user assembler files (with a ‘.s’ suffix) when assembling them.
Work around the 24K E48 (lost data on stores during refill) errata. The workarounds are implemented by the assembler rather than by GCC.
Work around certain R4000 CPU errata:
Work around certain R4400 CPU errata:
Work around certain R10000 errata:
scsequences may not behave atomically on revisions prior to 3.0. They may deadlock on revisions 2.6 and earlier.
This option can only be used if the target architecture supports branch-likely instructions. -mfix-r10000 is the default when -march=r10000 is used; -mno-fix-r10000 is the default otherwise.
Do not attempt to schedule the preceding instruction into the delay slot
of a branch instruction placed at the end of a short loop of six
instructions or fewer and always schedule a
nop instruction there
instead. The short loop bug under certain conditions causes loops to
execute only once or twice, due to a hardware bug in the R5900 chip. The
workaround is implemented by the assembler rather than by GCC.
Work around the RM7000
dmultu errata. The
workarounds are implemented by the assembler rather than by GCC.
Work around certain VR4120 errata:
dmultudoes not always produce the correct result.
ddivdo not always produce the correct result if one of the operands is negative.
The workarounds for the division errata rely on special functions in
libgcc.a. At present, these functions are only provided by
Other VR4120 errata require a NOP to be inserted between certain pairs of instructions. These errata are handled by the assembler, not by GCC itself.
Work around the VR4130
mfhi errata. The
workarounds are implemented by the assembler rather than by GCC,
although GCC avoids using
mfhi if the
instructions are available instead.
Work around certain SB-1 CPU core errata. (This flag currently works around the SB-1 revision 2 “F1” and “F2” floating-point errata.)
Specify whether GCC should insert cache barriers to avoid the side effects of speculation on R10K processors.
In common with many processors, the R10K tries to predict the outcome of a conditional branch and speculatively executes instructions from the “taken” branch. It later aborts these instructions if the predicted outcome is wrong. However, on the R10K, even aborted instructions can have side effects.
This problem only affects kernel stores and, depending on the system, kernel loads. As an example, a speculatively-executed store may load the target memory into cache and mark the cache line as dirty, even if the store itself is later aborted. If a DMA operation writes to the same area of memory before the “dirty” line is flushed, the cached data overwrites the DMA-ed data. See the R10K processor manual for a full description, including other potential problems.
One workaround is to insert cache barrier instructions before every memory access that might be speculatively executed and that might have side effects even if aborted. -mr10k-cache-barrier=setting controls GCC’s implementation of this workaround. It assumes that aborted accesses to any byte in the following regions does not have side effects:
It is the kernel’s responsibility to ensure that speculative accesses to these regions are indeed safe.
If the input program contains a function declaration such as:
void foo (void);
then the implementation of
foo must allow
j foo and
jal foo to be executed speculatively. GCC honors this
restriction for functions it compiles itself. It expects non-GCC
functions (such as hand-written assembly code) to do the same.
The option has three forms:
Insert a cache barrier before a load or store that might be speculatively executed and that might have side effects even if aborted.
Insert a cache barrier before a store that might be speculatively executed and that might have side effects even if aborted.
Disable the insertion of cache barriers. This is the default setting.
Specifies the function to call to flush the I and D caches, or to not
call any such function. If called, the function must take the same
arguments as the common
_flush_func, that is, the address of the
memory range for which the cache is being flushed, the size of the
memory range, and the number 3 (to flush both caches). The default
depends on the target GCC was configured for, but commonly is either
Set the cost of branches to roughly num “simple” instructions. This cost is only a heuristic and is not guaranteed to produce consistent results across releases. A zero cost redundantly selects the default, which is based on the -mtune setting.
Enable or disable use of Branch Likely instructions, regardless of the default for the selected architecture. By default, Branch Likely instructions may be generated if they are supported by the selected architecture. An exception is for the MIPS32 and MIPS64 architectures and processors that implement those architectures; for those, Branch Likely instructions are not be generated by default because the MIPS32 and MIPS64 architectures specifically deprecate their use.
These options control which form of branches will be generated. The default is -mcompact-branches=optimal.
The -mcompact-branches=never option ensures that compact branch instructions will never be generated.
The -mcompact-branches=always option ensures that a compact branch instruction will be generated if available for MIPS Release 6 onwards. If a compact branch instruction is not available (or pre-R6), a delay slot form of the branch will be used instead.
If it is used for MIPS16/microMIPS targets, it will be just ignored now. The behaviour for MIPS16/microMIPS may change in future, since they do have some compact branch instructions.
The -mcompact-branches=optimal option will cause a delay slot branch to be used if one is available in the current ISA and the delay slot is successfully filled. If the delay slot is not filled, a compact branch will be chosen if one is available.
Specifies whether FP exceptions are enabled. This affects how FP instructions are scheduled for some processors. The default is that FP exceptions are enabled.
For instance, on the SB-1, if FP exceptions are disabled, and we are emitting 64-bit code, then we can use both FP pipes. Otherwise, we can only use one FP pipe.
The VR4130 pipeline is two-way superscalar, but can only issue two instructions together if the first one is 8-byte aligned. When this option is enabled, GCC aligns pairs of instructions that it thinks should execute in parallel.
This option only has an effect when optimizing for the VR4130. It normally makes code faster, but at the expense of making it bigger. It is enabled by default at optimization level -O3.
Enable (disable) generation of
synci instructions on
architectures that support it. The
synci instructions (if
enabled) are generated when
This option defaults to -mno-synci, but the default can be overridden by configuring GCC with --with-synci.
When compiling code for single processor systems, it is generally safe
synci. However, on many multi-core (SMP) systems, it
does not invalidate the instruction caches on all cores and may lead
to undefined behavior.
Try to turn PIC calls that are normally dispatched via register
$25 into direct calls. This is only possible if the linker can
resolve the destination at link time and if the destination is within
range for a direct call.
-mrelax-pic-calls is the default if GCC was configured to use
an assembler and a linker that support the
directive and -mexplicit-relocs is in effect. With
-mno-explicit-relocs, this optimization can be performed by the
assembler and the linker alone without help from the compiler.
Emit (do not emit) code that allows
_mcount to modify the
calling function’s return address. When enabled, this option extends
_mcount interface with a new ra-address
parameter, which has type
intptr_t * and is passed in register
_mcount can then modify the return address by
doing both of the following:
*ra-address, if ra-address is nonnull.
The default is -mno-mcount-ra-address.
Enable (disable) frame header optimization in the o32 ABI. When using the o32 ABI, calling functions will allocate 16 bytes on the stack for the called function to write out register arguments. When enabled, this optimization will suppress the allocation of the frame header if it can be determined that it is unused.
This optimization is off by default at all optimization levels.
When applicable, enable (disable) the generation of
sdxc1 instructions. Enabled by default.
When applicable, enable (disable) the generation of 4-operand
madd.d and related instructions. Enabled by default.