These ‘-m’ options are defined for the IBM RS/6000 and PowerPC:
You use these options to specify which instructions are available on the processor you are using. The default value of these options is determined when configuring GCC. Specifying the -mcpu=cpu_type overrides the specification of these options. We recommend you use the -mcpu=cpu_type option rather than the options listed above.
Specifying -mpowerpc-gpopt allows GCC to use the optional PowerPC architecture instructions in the General Purpose group, including floating-point square root. Specifying -mpowerpc-gfxopt allows GCC to use the optional PowerPC architecture instructions in the Graphics group, including floating-point select.
The -mmfcrf option allows GCC to generate the move from condition register field instruction implemented on the POWER4 processor and other processors that support the PowerPC V2.01 architecture. The -mpopcntb option allows GCC to generate the popcount and double-precision FP reciprocal estimate instruction implemented on the POWER5 processor and other processors that support the PowerPC V2.02 architecture. The -mpopcntd option allows GCC to generate the popcount instruction implemented on the POWER7 processor and other processors that support the PowerPC V2.06 architecture. The -mfprnd option allows GCC to generate the FP round to integer instructions implemented on the POWER5+ processor and other processors that support the PowerPC V2.03 architecture. The -mcmpb option allows GCC to generate the compare bytes instruction implemented on the POWER6 processor and other processors that support the PowerPC V2.05 architecture. The -mmfpgpr option allows GCC to generate the FP move to/from general-purpose register instructions implemented on the POWER6X processor and other processors that support the extended PowerPC V2.05 architecture. The -mhard-dfp option allows GCC to generate the decimal floating-point instructions implemented on some POWER processors.
The -mpowerpc64 option allows GCC to generate the additional 64-bit instructions that are found in the full PowerPC64 architecture and to treat GPRs as 64-bit, doubleword quantities. GCC defaults to -mno-powerpc64.
Set architecture type, register usage, and instruction scheduling parameters for machine type cpu_type. Supported values for cpu_type are ‘401’, ‘403’, ‘405’, ‘405fp’, ‘440’, ‘440fp’, ‘464’, ‘464fp’, ‘476’, ‘476fp’, ‘505’, ‘601’, ‘602’, ‘603’, ‘603e’, ‘604’, ‘604e’, ‘620’, ‘630’, ‘740’, ‘7400’, ‘7450’, ‘750’, ‘801’, ‘821’, ‘823’, ‘860’, ‘970’, ‘8540’, ‘a2’, ‘e300c2’, ‘e300c3’, ‘e500mc’, ‘e500mc64’, ‘e5500’, ‘e6500’, ‘ec603e’, ‘G3’, ‘G4’, ‘G5’, ‘titan’, ‘power3’, ‘power4’, ‘power5’, ‘power5+’, ‘power6’, ‘power6x’, ‘power7’, ‘power8’, ‘power9’, ‘powerpc’, ‘powerpc64’, ‘powerpc64le’, and ‘rs64’.
-mcpu=powerpc, -mcpu=powerpc64, and -mcpu=powerpc64le specify pure 32-bit PowerPC (either endian), 64-bit big endian PowerPC and 64-bit little endian PowerPC architecture machine types, with an appropriate, generic processor model assumed for scheduling purposes.
The other options specify a specific processor. Code generated under those options runs best on that processor, and may not run at all on others.
The -mcpu options automatically enable or disable the following options:
-maltivec -mfprnd -mhard-float -mmfcrf -mmultiple -mpopcntb -mpopcntd -mpowerpc64 -mpowerpc-gpopt -mpowerpc-gfxopt -msingle-float -mdouble-float -msimple-fpu -mstring -mmulhw -mdlmzb -mmfpgpr -mvsx -mcrypto -mdirect-move -mhtm -mpower8-fusion -mpower8-vector -mquad-memory -mquad-memory-atomic -mfloat128 -mfloat128-hardware
The particular options set for any particular CPU varies between compiler versions, depending on what setting seems to produce optimal code for that CPU; it doesn’t necessarily reflect the actual hardware’s capabilities. If you wish to set an individual option to a particular value, you may specify it after the -mcpu option, like -mcpu=970 -mno-altivec.
On AIX, the -maltivec and -mpowerpc64 options are not enabled or disabled by the -mcpu option at present because AIX does not have full support for these options. You may still enable or disable them individually if you’re sure it’ll work in your environment.
Set the instruction scheduling parameters for machine type cpu_type, but do not set the architecture type or register usage, as -mcpu=cpu_type does. The same values for cpu_type are used for -mtune as for -mcpu. If both are specified, the code generated uses the architecture and registers set by -mcpu, but the scheduling parameters set by -mtune.
Generate PowerPC64 code for the small model: The TOC is limited to 64k.
Generate PowerPC64 code for the medium model: The TOC and other static data may be up to a total of 4G in size.
Generate PowerPC64 code for the large model: The TOC may be up to 4G in size. Other data and code is only limited by the 64-bit address space.
Generate code that uses (does not use) AltiVec instructions, and also enable the use of built-in functions that allow more direct access to the AltiVec instruction set. You may also need to set -mabi=altivec to adjust the current ABI with AltiVec ABI enhancements.
When -maltivec is used, rather than -maltivec=le or
-maltivec=be, the element order for AltiVec intrinsics such
match array element order corresponding to the endianness of the
target. That is, element zero identifies the leftmost element in a
vector register when targeting a big-endian platform, and identifies
the rightmost element in a vector register when targeting a
Generate AltiVec instructions using big-endian element order, regardless of whether the target is big- or little-endian. This is the default when targeting a big-endian platform.
The element order is used to interpret element numbers in AltiVec
intrinsics such as
vec_insert. By default, these match array element order
corresponding to the endianness for the target.
Generate AltiVec instructions using little-endian element order, regardless of whether the target is big- or little-endian. This is the default when targeting a little-endian platform. This option is currently ignored when targeting a big-endian platform.
The element order is used to interpret element numbers in AltiVec
intrinsics such as
vec_insert. By default, these match array element order
corresponding to the endianness for the target.
Generate VRSAVE instructions when generating AltiVec code.
Generate Cell microcode instructions.
Warn when a Cell microcode instruction is emitted. An example of a Cell microcode instruction is a variable shift.
Generate code that allows
to build executables and shared
libraries with non-executable
This is a PowerPC
32-bit SYSV ABI option.
Generate code that uses a BSS
.plt section that
fills in, and
sections that are both writable and executable.
This is a PowerPC 32-bit SYSV ABI option.
This switch enables or disables the generation of ISEL instructions.
This switch has been deprecated. Use -misel and -mno-isel instead.
Enable Local Register Allocation. This is still experimental for PowerPC, so by default the compiler uses standard reload (i.e. -mno-lra).
This switch enables or disables the generation of SPE simd instructions.
This switch enables or disables the generation of PAIRED simd instructions.
This option has been deprecated. Use -mspe and -mno-spe instead.
Generate code that uses (does not use) vector/scalar (VSX) instructions, and also enable the use of built-in functions that allow more direct access to the VSX instruction set.
Enable the use (disable) of the built-in functions that allow direct access to the cryptographic instructions that were added in version 2.07 of the PowerPC ISA.
Generate code that uses (does not use) the instructions to move data between the general purpose registers and the vector/scalar (VSX) registers that were added in version 2.07 of the PowerPC ISA.
Enable (disable) the use of the built-in functions that allow direct access to the Hardware Transactional Memory (HTM) instructions that were added in version 2.07 of the PowerPC ISA.
Generate code that keeps (does not keeps) some integer operations adjacent so that the instructions can be fused together on power8 and later processors.
Generate code that uses (does not use) the vector and scalar instructions that were added in version 2.07 of the PowerPC ISA. Also enable the use of built-in functions that allow more direct access to the vector instructions.
Generate code that uses (does not use) the non-atomic quad word memory instructions. The -mquad-memory option requires use of 64-bit mode.
Generate code that uses (does not use) the atomic quad word memory instructions. The -mquad-memory-atomic option requires use of 64-bit mode.
Generate code that uses (does not use) the scalar double precision instructions that target all 64 registers in the vector/scalar floating point register set that were added in version 2.06 of the PowerPC ISA. -mupper-regs-df is turned on by default if you use any of the -mcpu=power7, -mcpu=power8, or -mvsx options.
Generate code that uses (does not use) the scalar single precision instructions that target all 64 registers in the vector/scalar floating point register set that were added in version 2.07 of the PowerPC ISA. -mupper-regs-sf is turned on by default if you use either of the -mcpu=power8, -mpower8-vector, or -mcpu=power9 options.
Generate code that uses (does not use) the scalar instructions that target all 64 registers in the vector/scalar floating point register set, depending on the model of the machine.
If the -mno-upper-regs option is used, it turns off both -mupper-regs-sf and -mupper-regs-df options.
Enable/disable the __float128 keyword for IEEE 128-bit floating point and use either software emulation for IEEE 128-bit floating point or hardware instructions.
The VSX instruction set (-mvsx, -mcpu=power7, or -mcpu=power8) must be enabled to use the -mfloat128 option. The -mfloat128 option only works on PowerPC 64-bit Linux systems.
If you use the ISA 3.0 instruction set (-mcpu=power9), the -mfloat128 option will also enable the generation of ISA 3.0 IEEE 128-bit floating point instructions. Otherwise, IEEE 128-bit floating point will be done with software emulation.
Enable/disable using ISA 3.0 hardware instructions to support the __float128 data type.
If you use -mfloat128-hardware, it will enable the option -mfloat128 as well.
If you select ISA 3.0 instructions with -mcpu=power9, but do not use either -mfloat128 or -mfloat128-hardware, the IEEE 128-bit floating point support will not be enabled.
This switch enables or disables the generation of floating-point operations on the general-purpose registers for architectures that support it.
The argument ‘yes’ or ‘single’ enables the use of single-precision floating-point operations.
The argument ‘double’ enables the use of single and double-precision floating-point operations.
The argument ‘no’ disables floating-point operations on the general-purpose registers.
This option is currently only available on the MPC854x.
Generate code for 32-bit or 64-bit environments of Darwin and SVR4 targets (including GNU/Linux). The 32-bit environment sets int, long and pointer to 32 bits and generates code that runs on any PowerPC variant. The 64-bit environment sets int to 32 bits and long and pointer to 64 bits, and generates code for PowerPC64, as for -mpowerpc64.
Modify generation of the TOC (Table Of Contents), which is created for every executable file. The -mfull-toc option is selected by default. In that case, GCC allocates at least one TOC entry for each unique non-automatic variable reference in your program. GCC also places floating-point constants in the TOC. However, only 16,384 entries are available in the TOC.
If you receive a linker error message that saying you have overflowed the available TOC space, you can reduce the amount of TOC space used with the -mno-fp-in-toc and -mno-sum-in-toc options. -mno-fp-in-toc prevents GCC from putting floating-point constants in the TOC and -mno-sum-in-toc forces GCC to generate code to calculate the sum of an address and a constant at run time instead of putting that sum into the TOC. You may specify one or both of these options. Each causes GCC to produce very slightly slower and larger code at the expense of conserving TOC space.
If you still run out of space in the TOC even when you specify both of these options, specify -mminimal-toc instead. This option causes GCC to make only one TOC entry for every file. When you specify this option, GCC produces code that is slower and larger but which uses extremely little TOC space. You may wish to use this option only on files that contain less frequently-executed code.
Enable 64-bit AIX ABI and calling convention: 64-bit pointers, 64-bit
long type, and the infrastructure needed to support them.
Specifying -maix64 implies -mpowerpc64,
while -maix32 disables the 64-bit ABI and
implies -mno-powerpc64. GCC defaults to -maix32.
Produce code that conforms more closely to IBM XL compiler semantics when using AIX-compatible ABI. Pass floating-point arguments to prototyped functions beyond the register save area (RSA) on the stack in addition to argument FPRs. Do not assume that most significant double in 128-bit long double value is properly rounded when comparing values and converting to double. Use XL symbol names for long double support routines.
The AIX calling convention was extended but not initially documented to handle an obscure K&R C case of calling a function that takes the address of its arguments with fewer arguments than declared. IBM XL compilers access floating-point arguments that do not fit in the RSA from the stack when a subroutine is compiled without optimization. Because always storing floating-point arguments on the stack is inefficient and rarely needed, this option is not enabled by default and only is necessary when calling subroutines compiled by IBM XL compilers without optimization.
Support IBM RS/6000 SP Parallel Environment (PE). Link an application written to use message passing with special startup code to enable the application to run. The system must have PE installed in the standard location (/usr/lpp/ppe.poe/), or the specs file must be overridden with the -specs= option to specify the appropriate directory location. The Parallel Environment does not support threads, so the -mpe option and the -pthread option are incompatible.
On AIX, 32-bit Darwin, and 64-bit PowerPC GNU/Linux, the option -malign-natural overrides the ABI-defined alignment of larger types, such as floating-point doubles, on their natural size-based boundary. The option -malign-power instructs GCC to follow the ABI-specified alignment rules. GCC defaults to the standard alignment defined in the ABI.
On 64-bit Darwin, natural alignment is the default, and -malign-power is not supported.
Generate code that does not use (uses) the floating-point register set. Software floating-point emulation is provided if you use the -msoft-float option, and pass the option to GCC when linking.
Generate code for single- or double-precision floating-point operations. -mdouble-float implies -msingle-float.
Do not generate
div instructions for hardware
Specify type of floating-point unit. Valid values for name are ‘sp_lite’ (equivalent to -msingle-float -msimple-fpu), ‘dp_lite’ (equivalent to -mdouble-float -msimple-fpu), ‘sp_full’ (equivalent to -msingle-float), and ‘dp_full’ (equivalent to -mdouble-float).
Perform optimizations for the floating-point unit on Xilinx PPC 405/440.
Generate code that uses (does not use) the load multiple word instructions and the store multiple word instructions. These instructions are generated by default on POWER systems, and not generated on PowerPC systems. Do not use -mmultiple on little-endian PowerPC systems, since those instructions do not work when the processor is in little-endian mode. The exceptions are PPC740 and PPC750 which permit these instructions in little-endian mode.
Generate code that uses (does not use) the load string instructions and the store string word instructions to save multiple registers and do small block moves. These instructions are generated by default on POWER systems, and not generated on PowerPC systems. Do not use -mstring on little-endian PowerPC systems, since those instructions do not work when the processor is in little-endian mode. The exceptions are PPC740 and PPC750 which permit these instructions in little-endian mode.
Generate code that uses (does not use) the load or store instructions that update the base register to the address of the calculated memory location. These instructions are generated by default. If you use -mno-update, there is a small window between the time that the stack pointer is updated and the address of the previous frame is stored, which means code that walks the stack frame across interrupts or signals may get corrupted data.
Generate code that tries to avoid (not avoid) the use of indexed load or store instructions. These instructions can incur a performance penalty on Power6 processors in certain situations, such as when stepping through large arrays that cross a 16M boundary. This option is enabled by default when targeting Power6 and disabled otherwise.
Generate code that uses (does not use) the floating-point multiply and accumulate instructions. These instructions are generated by default if hardware floating point is used. The machine-dependent -mfused-madd option is now mapped to the machine-independent -ffp-contract=fast option, and -mno-fused-madd is mapped to -ffp-contract=off.
Generate code that uses (does not use) the half-word multiply and multiply-accumulate instructions on the IBM 405, 440, 464 and 476 processors. These instructions are generated by default when targeting those processors.
Generate code that uses (does not use) the string-search ‘dlmzb’ instruction on the IBM 405, 440, 464 and 476 processors. This instruction is generated by default when targeting those processors.
On System V.4 and embedded PowerPC systems do not (do) force structures and unions that contain bit-fields to be aligned to the base type of the bit-field.
For example, by default a structure containing nothing but 8
unsigned bit-fields of length 1 is aligned to a 4-byte
boundary and has a size of 4 bytes. By using -mno-bit-align,
the structure is aligned to a 1-byte boundary and is 1 byte in
On System V.4 and embedded PowerPC systems do not (do) assume that unaligned memory references are handled by the system.
Generate code that allows (does not allow) a static executable to be
relocated to a different address at run time. A simple embedded
PowerPC system loader should relocate the entire contents of
.got2 and 4-byte locations listed in the
a table of 32-bit addresses generated by this option. For this to
work, all objects linked together must be compiled with
-mrelocatable or -mrelocatable-lib.
-mrelocatable code aligns the stack to an 8-byte boundary.
Like -mrelocatable, -mrelocatable-lib generates a
.fixup section to allow static executables to be relocated at
run time, but -mrelocatable-lib does not use the smaller stack
alignment of -mrelocatable. Objects compiled with
-mrelocatable-lib may be linked with objects compiled with
any combination of the -mrelocatable options.
On System V.4 and embedded PowerPC systems do not (do) assume that register 2 contains a pointer to a global area pointing to the addresses used in the program.
On System V.4 and embedded PowerPC systems compile code for the processor in little-endian mode. The -mlittle-endian option is the same as -mlittle.
On System V.4 and embedded PowerPC systems compile code for the processor in big-endian mode. The -mbig-endian option is the same as -mbig.
On Darwin and Mac OS X systems, compile code so that it is not relocatable, but that its external references are relocatable. The resulting code is suitable for applications, but not shared libraries.
Treat the register used for PIC addressing as read-only, rather than loading it in the prologue for each function. The runtime system is responsible for initializing this register with an appropriate value before execution begins.
This option controls the priority that is assigned to dispatch-slot restricted instructions during the second scheduling pass. The argument priority takes the value ‘0’, ‘1’, or ‘2’ to assign no, highest, or second-highest (respectively) priority to dispatch-slot restricted instructions.
This option controls which dependences are considered costly by the target during instruction scheduling. The argument dependence_type takes one of the following values:
No dependence is costly.
All dependences are costly.
A true dependence from store to load is costly.
Any dependence from store to load is costly.
Any dependence for which the latency is greater than or equal to number is costly.
This option controls which NOP insertion scheme is used during the second scheduling pass. The argument scheme takes one of the following values:
Don’t insert NOPs.
Pad with NOPs any dispatch group that has vacant issue slots, according to the scheduler’s grouping.
Insert NOPs to force costly dependent insns into separate groups. Insert exactly as many NOPs as needed to force an insn to a new group, according to the estimated processor grouping.
Insert NOPs to force costly dependent insns into separate groups. Insert number NOPs to force an insn to a new group.
On System V.4 and embedded PowerPC systems compile code using calling conventions that adhere to the March 1995 draft of the System V Application Binary Interface, PowerPC processor supplement. This is the default unless you configured GCC using ‘powerpc-*-eabiaix’.
Specify both -mcall-sysv and -meabi options.
Specify both -mcall-sysv and -mno-eabi options.
On System V.4 and embedded PowerPC systems compile code for the AIX operating system.
On System V.4 and embedded PowerPC systems compile code for the Linux-based GNU system.
On System V.4 and embedded PowerPC systems compile code for the FreeBSD operating system.
On System V.4 and embedded PowerPC systems compile code for the NetBSD operating system.
On System V.4 and embedded PowerPC systems compile code for the OpenBSD operating system.
Return all structures in memory (as specified by the AIX ABI).
Return structures smaller than 8 bytes in registers (as specified by the SVR4 ABI).
Extend the current ABI with a particular extension, or remove such extension. Valid values are ‘altivec’, ‘no-altivec’, ‘spe’, ‘no-spe’, ‘ibmlongdouble’, ‘ieeelongdouble’, ‘elfv1’, ‘elfv2’.
Extend the current ABI with SPE ABI extensions. This does not change the default ABI, instead it adds the SPE ABI extensions to the current ABI.
Disable Book-E SPE ABI extensions for the current ABI.
Change the current ABI to use IBM extended-precision long double. This is a PowerPC 32-bit SYSV ABI option.
Change the current ABI to use IEEE extended-precision long double. This is a PowerPC 32-bit Linux ABI option.
Change the current ABI to use the ELFv1 ABI. This is the default ABI for big-endian PowerPC 64-bit Linux. Overriding the default ABI requires special system support and is likely to fail in spectacular ways.
Change the current ABI to use the ELFv2 ABI. This is the default ABI for little-endian PowerPC 64-bit Linux. Overriding the default ABI requires special system support and is likely to fail in spectacular ways.
On System V.4 and embedded PowerPC systems assume that all calls to
variable argument functions are properly prototyped. Otherwise, the
compiler must insert an instruction before every non-prototyped call to
set or clear bit 6 of the condition code register (
indicate whether floating-point values are passed in the floating-point
registers in case the function takes variable arguments. With
-mprototype, only calls to prototyped variable argument functions
set or clear the bit.
On embedded PowerPC systems, assume that the startup module is called sim-crt0.o and that the standard C libraries are libsim.a and libc.a. This is the default for ‘powerpc-*-eabisim’ configurations.
On embedded PowerPC systems, assume that the startup module is called crt0.o and the standard C libraries are libmvme.a and libc.a.
On embedded PowerPC systems, assume that the startup module is called crt0.o and the standard C libraries are libads.a and libc.a.
On embedded PowerPC systems, assume that the startup module is called crt0.o and the standard C libraries are libyk.a and libc.a.
On System V.4 and embedded PowerPC systems, specify that you are compiling for a VxWorks system.
On embedded PowerPC systems, set the
PPC_EMB bit in the ELF flags
header to indicate that ‘eabi’ extended relocations are used.
On System V.4 and embedded PowerPC systems do (do not) adhere to the
Embedded Applications Binary Interface (EABI), which is a set of
modifications to the System V.4 specifications. Selecting -meabi
means that the stack is aligned to an 8-byte boundary, a function
__eabi is called from
main to set up the EABI
environment, and the -msdata option can use both
r13 to point to two separate small data areas. Selecting
-mno-eabi means that the stack is aligned to a 16-byte boundary,
no EABI initialization function is called from
main, and the
-msdata option only uses
r13 to point to a single
small data area. The -meabi option is on by default if you
configured GCC using one of the ‘powerpc*-*-eabi*’ options.
On System V.4 and embedded PowerPC systems, put small initialized
const global and static data in the
.sdata2 section, which
is pointed to by register
r2. Put small initialized
const global and static data in the
which is pointed to by register
r13. Put small uninitialized
global and static data in the
.sbss section, which is adjacent to
.sdata section. The -msdata=eabi option is
incompatible with the -mrelocatable option. The
-msdata=eabi option also sets the -memb option.
On System V.4 and embedded PowerPC systems, put small global and static
data in the
.sdata section, which is pointed to by register
r13. Put small uninitialized global and static data in the
.sbss section, which is adjacent to the
The -msdata=sysv option is incompatible with the
On System V.4 and embedded PowerPC systems, if -meabi is used, compile code the same as -msdata=eabi, otherwise compile code the same as -msdata=sysv.
On System V.4 and embedded PowerPC systems, put small global
data in the
.sdata section. Put small uninitialized global
data in the
.sbss section. Do not use register
to address small data however. This is the default behavior unless
other -msdata options are used.
On embedded PowerPC systems, put all initialized global and static data
.data section, and all uninitialized data in the
Inline all block moves (such as calls to
memcpy or structure
copies) less than or equal to num bytes. The minimum value for
num is 32 bytes on 32-bit targets and 64 bytes on 64-bit
targets. The default value is target-specific.
On embedded PowerPC systems, put global and static items less than or equal to num bytes into the small data or BSS sections instead of the normal data or BSS section. By default, num is 8. The -G num switch is also passed to the linker. All modules should be compiled with the same -G num value.
On System V.4 and embedded PowerPC systems do (do not) emit register names in the assembly language output using symbolic forms.
By default assume that all calls are far away so that a longer and more
expensive calling sequence is required. This is required for calls
farther than 32 megabytes (33,554,432 bytes) from the current location.
A short call is generated if the compiler knows
the call cannot be that far away. This setting can be overridden by
shortcall function attribute, or by
Some linkers are capable of detecting out-of-range calls and generating glue code on the fly. On these systems, long calls are unnecessary and generate slower code. As of this writing, the AIX linker can do this, as can the GNU linker for PowerPC/64. It is planned to add this feature to the GNU linker for 32-bit PowerPC systems as well.
On Darwin/PPC systems,
#pragma longcall generates
callee, L42, plus a branch island (glue code). The two target
addresses represent the callee and the branch island. The
Darwin/PPC linker prefers the first address and generates a
callee if the PPC
bl instruction reaches the callee directly;
otherwise, the linker generates
bl L42 to call the branch
island. The branch island is appended to the body of the
calling function; it computes the full 32-bit address of the callee
and jumps to it.
On Mach-O (Darwin) systems, this option directs the compiler emit to the glue for every direct call, and the Darwin linker decides whether to use or discard it.
In the future, GCC may ignore all longcall specifications when the linker is known to generate glue.
Mark (do not mark) calls to
__tls_get_addr with a relocation
specifying the function argument. The relocation allows the linker to
reliably associate function call with argument setup instructions for
TLS optimization, which in turn allows GCC to better schedule the
Adds support for multithreading with the pthreads library. This option sets flags for both the preprocessor and linker.
This option enables use of the reciprocal estimate and reciprocal square root estimate instructions with additional Newton-Raphson steps to increase precision instead of doing a divide or square root and divide for floating-point arguments. You should use the -ffast-math option when using -mrecip (or at least -funsafe-math-optimizations, -ffinite-math-only, -freciprocal-math and -fno-trapping-math). Note that while the throughput of the sequence is generally higher than the throughput of the non-reciprocal instruction, the precision of the sequence can be decreased by up to 2 ulp (i.e. the inverse of 1.0 equals 0.99999994) for reciprocal square roots.
This option controls which reciprocal estimate instructions
may be used. opt is a comma-separated list of options, which may
be preceded by a
! to invert the option:
Enable all estimate instructions.
Enable the default instructions, equivalent to -mrecip.
Disable all estimate instructions, equivalent to -mno-recip.
Enable the reciprocal approximation instructions for both single and double precision.
Enable the single-precision reciprocal approximation instructions.
Enable the double-precision reciprocal approximation instructions.
Enable the reciprocal square root approximation instructions for both single and double precision.
Enable the single-precision reciprocal square root approximation instructions.
Enable the double-precision reciprocal square root approximation instructions.
So, for example, -mrecip=all,!rsqrtd enables
all of the reciprocal estimate instructions, except for the
which handle the double-precision reciprocal square root calculations.
Assume (do not assume) that the reciprocal estimate instructions provide higher-precision estimates than is mandated by the PowerPC ABI. Selecting -mcpu=power6, -mcpu=power7 or -mcpu=power8 automatically selects -mrecip-precision. The double-precision square root estimate instructions are not generated by default on low-precision machines, since they do not provide an estimate that converges after three steps.
Specifies the ABI type to use for vectorizing intrinsics using an
external library. The only type supported at present is ‘mass’,
which specifies to use IBM’s Mathematical Acceleration Subsystem
(MASS) libraries for vectorizing intrinsics using external libraries.
GCC currently emits calls to
tanhf4 when generating code
for power7. Both -ftree-vectorize and
-funsafe-math-optimizations must also be enabled. The MASS
libraries must be specified at link time.
Generate (do not generate) the
friz instruction when the
-funsafe-math-optimizations option is used to optimize
rounding of floating-point values to 64-bit integer and back to floating
friz instruction does not return the same value if
the floating-point number is too large to fit in an integer.
Generate (do not generate) code to load up the static chain register
r11) when calling through a pointer on AIX and 64-bit Linux
systems where a function pointer points to a 3-word descriptor giving
the function address, TOC value to be loaded in register
static chain value to be loaded in register
-mpointers-to-nested-functions is on by default. You cannot
call through pointers to nested functions or pointers
to functions compiled in other languages that use the static chain if
you use -mno-pointers-to-nested-functions.
Generate (do not generate) code to save the TOC value in the reserved stack location in the function prologue if the function calls through a pointer on AIX and 64-bit Linux systems. If the TOC value is not saved in the prologue, it is saved just before the call through the pointer. The -mno-save-toc-indirect option is the default.
Generate (do not generate) code to pass structure parameters with a maximum alignment of 64 bits, for compatibility with older versions of GCC.
Older versions of GCC (prior to 4.9.0) incorrectly did not align a structure parameter on a 128-bit boundary when that structure contained a member requiring 128-bit alignment. This is corrected in more recent versions of GCC. This option may be used to generate code that is compatible with functions compiled with older versions of GCC.
The -mno-compat-align-parm option is the default.