These options are defined for AVR implementations:
-mmcu=
mcuThe default for this option is avr2
.
GCC supports the following AVR devices and ISAs:
avr2
attiny22
, attiny26
, at90c8534
, at90s2313
, at90s2323
, at90s2333
, at90s2343
, at90s4414
, at90s4433
, at90s4434
, at90s8515
, at90s8535
.
avr25
MOVW
instruction.
ata5272
, ata6289
, attiny13
, attiny13a
, attiny2313
, attiny2313a
, attiny24
, attiny24a
, attiny25
, attiny261
, attiny261a
, attiny43u
, attiny4313
, attiny44
, attiny44a
, attiny45
, attiny461
, attiny461a
, attiny48
, attiny84
, attiny84a
, attiny85
, attiny861
, attiny861a
, attiny87
, attiny88
, at86rf401
.
avr3
at43usb355
, at76c711
.
avr31
atmega103
, at43usb320
.
avr35
MOVW
instruction.
ata5505
, atmega16u2
, atmega32u2
, atmega8u2
, attiny1634
, attiny167
, at90usb162
, at90usb82
.
avr4
ata6285
, ata6286
, atmega48
, atmega48a
, atmega48p
, atmega48pa
, atmega8
, atmega8a
, atmega8hva
, atmega8515
, atmega8535
, atmega88
, atmega88a
, atmega88p
, atmega88pa
, at90pwm1
, at90pwm2
, at90pwm2b
, at90pwm3
, at90pwm3b
, at90pwm81
.
avr5
ata5790
, ata5790n
, ata5795
, atmega16
, atmega16a
, atmega16hva
, atmega16hva2
, atmega16hvb
, atmega16hvbrevb
, atmega16m1
, atmega16u4
, atmega161
, atmega162
, atmega163
, atmega164a
, atmega164p
, atmega164pa
, atmega165
, atmega165a
, atmega165p
, atmega165pa
, atmega168
, atmega168a
, atmega168p
, atmega168pa
, atmega169
, atmega169a
, atmega169p
, atmega169pa
, atmega26hvg
, atmega32
, atmega32a
, atmega32c1
, atmega32hvb
, atmega32hvbrevb
, atmega32m1
, atmega32u4
, atmega32u6
, atmega323
, atmega324a
, atmega324p
, atmega324pa
, atmega325
, atmega325a
, atmega325p
, atmega3250
, atmega3250a
, atmega3250p
, atmega3250pa
, atmega328
, atmega328p
, atmega329
, atmega329a
, atmega329p
, atmega329pa
, atmega3290
, atmega3290a
, atmega3290p
, atmega3290pa
, atmega406
, atmega48hvf
, atmega64
, atmega64a
, atmega64c1
, atmega64hve
, atmega64m1
, atmega64rfa2
, atmega64rfr2
, atmega640
, atmega644
, atmega644a
, atmega644p
, atmega644pa
, atmega645
, atmega645a
, atmega645p
, atmega6450
, atmega6450a
, atmega6450p
, atmega649
, atmega649a
, atmega649p
, atmega6490
, atmega6490a
, atmega6490p
, at90can32
, at90can64
, at90pwm161
, at90pwm216
, at90pwm316
, at90scr100
, at90usb646
, at90usb647
, at94k
, m3000
.
avr51
atmega128
, atmega128a
, atmega128rfa1
, atmega1280
, atmega1281
, atmega1284
, atmega1284p
, at90can128
, at90usb1286
, at90usb1287
.
avr6
atmega2560
, atmega2561
.
avrxmega2
atmxt112sl
, atmxt224
, atmxt224e
, atmxt336s
, atxmega16a4
, atxmega16a4u
, atxmega16c4
, atxmega16d4
, atxmega32a4
, atxmega32a4u
, atxmega32c4
, atxmega32d4
, atxmega32e5
, atxmega32x1
.
avrxmega4
atxmega64a3
, atxmega64a3u
, atxmega64a4u
, atxmega64b1
, atxmega64b3
, atxmega64c3
, atxmega64d3
, atxmega64d4
.
avrxmega5
atxmega64a1
, atxmega64a1u
.
avrxmega6
atmxt540s
, atmxt540sreva
, atxmega128a3
, atxmega128a3u
, atxmega128b1
, atxmega128b3
, atxmega128c3
, atxmega128d3
, atxmega128d4
, atxmega192a3
, atxmega192a3u
, atxmega192c3
, atxmega192d3
, atxmega256a3
, atxmega256a3b
, atxmega256a3bu
, atxmega256a3u
, atxmega256c3
, atxmega256d3
, atxmega384c3
, atxmega384d3
.
avrxmega7
atxmega128a1
, atxmega128a1u
, atxmega128a4u
.
avr1
attiny11
, attiny12
, attiny15
, attiny28
, at90s1200
.
-maccumulate-args
Popping the arguments after the function call can be expensive on AVR so that accumulating the stack space might lead to smaller executables because arguments need not to be removed from the stack after such a function call.
This option can lead to reduced code size for functions that perform
several calls to functions that get their arguments on the stack like
calls to printf-like functions.
-mbranch-cost=
cost-mcall-prologues
-mint8
int
to be 8-bit integer. This affects the sizes of all types: a
char
is 1 byte, an int
is 1 byte, a long
is 2 bytes,
and long long
is 4 bytes. Please note that this option does not
conform to the C standards, but it results in smaller code
size.
-mno-interrupts
-mrelax
CALL
resp. JMP
instruction by the shorter
RCALL
resp. RJMP
instruction if applicable.
Setting -mrelax
just adds the --relax
option to the
linker command line when the linker is called.
Jump relaxing is performed by the linker because jump offsets are not known before code is located. Therefore, the assembler code generated by the compiler is the same, but the instructions in the executable may differ from instructions in the assembler code.
Relaxing must be turned on if linker stubs are needed, see the
section on EIND
and linker stubs below.
-msp8
This option is used internally by the compiler to select and
build multilibs for architectures avr2
and avr25
.
These architectures mix devices with and without SPH
.
For any setting other than -mmcu=avr2
or -mmcu=avr25
the compiler driver will add or remove this option from the compiler
proper's command line, because the compiler then knows if the device
or architecture has an 8-bit stack pointer and thus no SPH
register or not.
-mstrict-X
X
in a way proposed by the hardware. This means
that X
is only used in indirect, post-increment or
pre-decrement addressing.
Without this option, the X
register may be used in the same way
as Y
or Z
which then is emulated by additional
instructions.
For example, loading a value with X+const
addressing with a
small non-negative const < 64
to a register Rn is
performed as
adiw r26, const ; X += const ld Rn, X ; Rn = *X sbiw r26, const ; X -= const
-mtiny-stack
-Waddr-space-convert
EIND
and Devices with more than 128 Ki Bytes of FlashPointers in the implementation are 16 bits wide. The address of a function or label is represented as word address so that indirect jumps and calls can target any code address in the range of 64 Ki words.
In order to facilitate indirect jump on devices with more than 128 Ki
bytes of program memory space, there is a special function register called
EIND
that serves as most significant part of the target address
when EICALL
or EIJMP
instructions are used.
Indirect jumps and calls on these devices are handled as follows by the compiler and are subject to some limitations:
EIND
.
EIND
implicitely in EICALL
/EIJMP
instructions or might read EIND
directly in order to emulate an
indirect call/jump by means of a RET
instruction.
EIND
never changes during the startup
code or during the application. In particular, EIND
is not
saved/restored in function or interrupt service routine
prologue/epilogue.
-mrelax
and the linler option --relax
.
There are corner cases where the linker is supposed to generate stubs
but aborts without relaxation and without a helpful error message.
EIND = 0
.
If code is supposed to work for a setup with EIND != 0
, a custom
linker script has to be used in order to place the sections whose
name start with .trampolines
into the segment where EIND
points to.
EIND
.
Notice that startup code is a blend of code from libgcc and AVR-LibC.
For the impact of AVR-LibC on EIND
, see the
AVR-LibC user manual.
EIND
early, for example by means of initialization code located in
section .init3
. Such code runs prior to general startup code
that initializes RAM and calls constructors, but after the bit
of startup code from AVR-LibC that sets EIND
to the segment
where the vector table is located.
#include <avr/io.h> static void __attribute__((section(".init3"),naked,used,no_instrument_function)) init3_set_eind (void) { __asm volatile ("ldi r24,pm_hh8(__trampolines_start)\n\t" "out %i0,r24" :: "n" (&EIND) : "r24","memory"); }
The __trampolines_start
symbol is defined in the linker script.
gs
modifier
(short for generate stubs) like so:
LDI r24, lo8(gs(func)) LDI r25, hi8(gs(func))
gs
modifiers for code labels in the
following situations:
gs()
modifier explained above.
int main (void) { /* Call function at word address 0x2 */ return ((int(*)(void)) 0x2)(); }
Instead, a stub has to be set up, i.e. the function has to be called
through a symbol (func_4
in the example):
int main (void) { extern int func_4 (void); /* Call function at byte address 0x4 */ return func_4(); }
and the application be linked with -Wl,--defsym,func_4=0x4
.
Alternatively, func_4
can be defined in the linker script.
RAMPD
, RAMPX
, RAMPY
and RAMPZ
Special Function RegistersSome AVR devices support memories larger than the 64 KiB range
that can be accessed with 16-bit pointers. To access memory locations
outside this 64 KiB range, the contentent of a RAMP
register is used as high part of the address:
The X
, Y
, Z
address register is concatenated
with the RAMPX
, RAMPY
, RAMPZ
special function
register, respectively, to get a wide address. Similarly,
RAMPD
is used together with direct addressing.
RAMP
special function
registers with zero.
__flash
is used, then RAMPZ
is set
as needed before the operation.
RAMPZ
to accomplish an operation, RAMPZ
is reset to zero after the operation.
RAMP
register, the ISR
prologue/epilogue saves/restores that SFR and initializes it with
zero in case the ISR code might (implicitly) use it.
RAMP
registers,
you must reset it to zero after the access.
GCC defines several built-in macros so that the user code can test
for the presence or absence of features. Almost any of the following
built-in macros are deduced from device capabilities and thus
triggered by the -mmcu=
command-line option.
For even more AVR-specific built-in macros see AVR Named Address Spaces and AVR Built-in Functions.
__AVR_ARCH__
-mmcu=
mcu option.
Possible values are:
2
, 25
, 3
, 31
, 35
,
4
, 5
, 51
, 6
, 102
, 104
,
105
, 106
, 107
for mcu=avr2
, avr25
, avr3
,
avr31
, avr35
, avr4
, avr5
, avr51
,
avr6
, avrxmega2
, avrxmega4
, avrxmega5
,
avrxmega6
, avrxmega7
, respectively.
If mcu specifies a device, this built-in macro is set
accordingly. For example, with -mmcu=atmega8
the macro will be
defined to 4
.
__AVR_
Device__
-mmcu=
device defines this built-in macro which reflects
the device's name. For example, -mmcu=atmega8
defines the
built-in macro __AVR_ATmega8__
, -mmcu=attiny261a
defines
__AVR_ATtiny261A__
, etc.
The built-in macros' names follow
the scheme __AVR_
Device__
where Device is
the device name as from the AVR user manual. The difference between
Device in the built-in macro and device in
-mmcu=
device is that the latter is always lowercase.
If device is not a device but only a core architecture like
avr51
, this macro will not be defined.
__AVR_XMEGA__
__AVR_HAVE_ELPM__
ELPM
instruction.
__AVR_HAVE_ELPMX__
ELPM R
n,Z
and ELPM
R
n,Z+
instructions.
__AVR_HAVE_MOVW__
MOVW
instruction to perform 16-bit
register-register moves.
__AVR_HAVE_LPMX__
LPM R
n,Z
and
LPM R
n,Z+
instructions.
__AVR_HAVE_MUL__
__AVR_HAVE_JMP_CALL__
JMP
and CALL
instructions.
This is the case for devices with at least 16 KiB of program
memory.
__AVR_HAVE_EIJMP_EICALL__
__AVR_3_BYTE_PC__
EIJMP
and EICALL
instructions.
This is the case for devices with more than 128 KiB of program memory.
This also means that the program counter
(PC) is 3 bytes wide.
__AVR_2_BYTE_PC__
__AVR_HAVE_8BIT_SP__
__AVR_HAVE_16BIT_SP__
-mtiny-stack
.
__AVR_HAVE_SPH__
__AVR_SP8__
-mmcu=
and
in the cases of -mmcu=avr2
and -mmcu=avr25
also
by -msp8
.
__AVR_HAVE_RAMPD__
__AVR_HAVE_RAMPX__
__AVR_HAVE_RAMPY__
__AVR_HAVE_RAMPZ__
RAMPD
, RAMPX
, RAMPY
,
RAMPZ
special function register, respectively.
__NO_INTERRUPTS__
-mno-interrupts
command line option.
__AVR_ERRATA_SKIP__
__AVR_ERRATA_SKIP_JMP_CALL__
SBRS
, SBRC
, SBIS
, SBIC
and CPSE
.
The second macro is only defined if __AVR_HAVE_JMP_CALL__
is also
set.
__AVR_ISA_RMW__
__AVR_SFR_OFFSET__=
offsetIN
, OUT
, SBI
, etc. may use a different
address as if addressed by an instruction to access RAM like LD
or STS
. This offset depends on the device architecture and has
to be subtracted from the RAM address in order to get the
respective I/O address.
__WITH_AVRLIBC__
--with-avrlibc
configure option.