10.18.8.3 Drawbacks of the old pipeline description
The old instruction level parallelism description and the pipeline
hazards recognizer based on it have the following drawbacks in
comparison with the DFA-based ones:
- Each functional unit is believed to be reserved at the instruction
execution start. This is a very inaccurate model for modern
- An inadequate description of instruction latency times. The latency
time is bound with a functional unit reserved by an instruction not
with the instruction itself. In other words, the description is
oriented to describe at most one unit reservation by each instruction.
It also does not permit to describe special bypasses between
- The implementation of the pipeline hazard recognizer interface has
constraints on number of functional units. This is a number of bits
in integer on the host machine.
- The interface to the pipeline hazard recognizer is more complex than
one to the automaton based pipeline recognizer.
- An unnatural description when you write a unit and a condition which
selects instructions using the unit. Writing all unit reservations
for an instruction (an instruction class) is more natural.
- The recognition of the interlock delays has a slow implementation. The GCC
scheduler supports structures which describe the unit reservations.
The more functional units a processor has, the slower its pipeline hazard
recognizer will be. Such an implementation would become even slower when we
reserve functional units not only at the instruction execution start.
In an automaton based pipeline hazard recognizer, speed is not dependent
on processor complexity.