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S/390: Enable HANDLE_DIVIDE_OVERFLOW
- From: Ulrich Weigand <weigand at i1 dot informatik dot uni-erlangen dot de>
- To: gcc-patches at gcc dot gnu dot org, java-patches at gcc dot gnu dot org
- Date: Wed, 14 Jul 2004 15:10:39 +0200 (CEST)
- Subject: S/390: Enable HANDLE_DIVIDE_OVERFLOW
Hello,
now that we use SIGINFO-type signal handlers in libjava, it is
possible to finally implement HANDLE_DIVIDE_OVERFLOW for s390
and s390x targets.
The patch below does this; it passes the Divide_1 testcase without
regressions. However, testing this uncovered a bug in the s390
compiler backend where the code that emulated unsigned divide using
a signed divide instruction would *not* generate a trap for division
by zero. This is also fixed below.
Bootstrapped/regtested on s390-ibm-linux and s390x-ibm-linux,
applied to mainline.
Bye,
Ulrich
gcc/ChangeLog:
* config/s390/s390.md ("udivsi3"): Ensure trap is generated
for division by zero.
("umodsi3"): Likewise.
libjava/ChangeLog:
* configure.host (DIVIDESPEC) [s390*-*-*]: Set to
-fno-use-divide-subroutine.
* include/s390-signal.h: Include <ucontext.h> and <limits.h>.
(HANDLE_FPE): Define.
(SIGNAL_HANDLER): Change third argument to ucontext_t *.
(struct old_s390_kernel_sigaction): Likewise for k_sa_handler.
(HANDLE_DIVIDE_OVERFLOW): Define.
Index: gcc/config/s390/s390.md
===================================================================
RCS file: /cvs/gcc/gcc/gcc/config/s390/s390.md,v
retrieving revision 1.116
diff -c -p -r1.116 s390.md
*** gcc/config/s390/s390.md 7 Jul 2004 19:24:47 -0000 1.116
--- gcc/config/s390/s390.md 14 Jul 2004 01:08:01 -0000
***************
*** 4990,4996 ****
emit_move_insn (operands[0], const0_rtx);
emit_insn (gen_cmpsi (operands[2], operands[1]));
emit_jump_insn (gen_bgtu (label3));
! emit_insn (gen_cmpsi (operands[2], const1_rtx));
emit_jump_insn (gen_blt (label2));
emit_insn (gen_cmpsi (operands[2], const1_rtx));
emit_jump_insn (gen_beq (label1));
--- 4990,4996 ----
emit_move_insn (operands[0], const0_rtx);
emit_insn (gen_cmpsi (operands[2], operands[1]));
emit_jump_insn (gen_bgtu (label3));
! emit_insn (gen_cmpsi (operands[2], const0_rtx));
emit_jump_insn (gen_blt (label2));
emit_insn (gen_cmpsi (operands[2], const1_rtx));
emit_jump_insn (gen_beq (label1));
***************
*** 5082,5088 ****
emit_move_insn(operands[0], operands[1]);
emit_insn (gen_cmpsi (operands[2], operands[1]));
emit_jump_insn (gen_bgtu (label3));
! emit_insn (gen_cmpsi (operands[2], const1_rtx));
emit_jump_insn (gen_blt (label2));
emit_insn (gen_cmpsi (operands[2], const1_rtx));
emit_jump_insn (gen_beq (label1));
--- 5082,5088 ----
emit_move_insn(operands[0], operands[1]);
emit_insn (gen_cmpsi (operands[2], operands[1]));
emit_jump_insn (gen_bgtu (label3));
! emit_insn (gen_cmpsi (operands[2], const0_rtx));
emit_jump_insn (gen_blt (label2));
emit_insn (gen_cmpsi (operands[2], const1_rtx));
emit_jump_insn (gen_beq (label1));
Index: libjava/configure.host
===================================================================
RCS file: /cvs/gcc/gcc/libjava/configure.host,v
retrieving revision 1.60
diff -c -p -r1.60 configure.host
*** libjava/configure.host 9 Jul 2004 03:39:31 -0000 1.60
--- libjava/configure.host 14 Jul 2004 01:08:10 -0000
*************** case "${host}" in
*** 138,143 ****
--- 138,144 ----
s390*-*)
sysdeps_dir=s390
libgcj_interpreter=yes
+ DIVIDESPEC=-fno-use-divide-subroutine
enable_hash_synchronization_default=yes
;;
sparc*-*)
Index: libjava/include/s390-signal.h
===================================================================
RCS file: /cvs/gcc/gcc/libjava/include/s390-signal.h,v
retrieving revision 1.3
diff -c -p -r1.3 s390-signal.h
*** libjava/include/s390-signal.h 11 Jul 2004 11:49:25 -0000 1.3
--- libjava/include/s390-signal.h 14 Jul 2004 01:08:12 -0000
*************** details. */
*** 15,32 ****
#include <signal.h>
#include <sys/syscall.h>
#define HANDLE_SEGV 1
! #undef HANDLE_FPE
#define SIGNAL_HANDLER(_name) \
! static void _name (int, siginfo_t *, void *)
/* We no longer need to fiddle with the PSW address in the signal handler;
this is now all handled correctly in MD_FALLBACK_FRAME_STATE_FOR. */
#define MAKE_THROW_FRAME(_exception)
/* For an explanation why we cannot simply use sigaction to
install the handlers, see i386-signal.h. */
--- 15,184 ----
#include <signal.h>
#include <sys/syscall.h>
+ #include <ucontext.h>
+ #include <limits.h>
#define HANDLE_SEGV 1
! #define HANDLE_FPE 1
#define SIGNAL_HANDLER(_name) \
! static void _name (int, siginfo_t *_si __attribute__((unused)), \
! ucontext_t *_uc __attribute__((unused)))
/* We no longer need to fiddle with the PSW address in the signal handler;
this is now all handled correctly in MD_FALLBACK_FRAME_STATE_FOR. */
#define MAKE_THROW_FRAME(_exception)
+ /* According to the JVM spec, "if the dividend is the negative integer
+ of the smallest magnitude and the divisor is -1, then overflow occurs
+ and the result is equal to the dividend. Despite the overflow, no
+ exception occurs".
+
+ We handle this by inspecting the instruction which generated the signal,
+ and if dividend and divisor are as above, we simply return from the signal
+ handler. This causes execution to continue after the instruction.
+ Before returning, we the set result registers as expected. */
+
+ #define HANDLE_DIVIDE_OVERFLOW \
+ do \
+ { \
+ unsigned char *_eip = (unsigned char *) \
+ __builtin_extract_return_addr (_si->si_addr); \
+ unsigned long *_regs = _uc->uc_mcontext.gregs; \
+ int _r1, _r2, _d2, _x2, _b2; \
+ \
+ /* First, a couple of helper routines to decode instructions. */ \
+ struct _decode \
+ { \
+ /* Decode RR instruction format. */ \
+ static inline int _is_rr (unsigned char *_eip, \
+ unsigned char _op, \
+ int *_r1, int *_r2) \
+ { \
+ if (_eip[0] == _op) \
+ { \
+ *_r1 = _eip[1] >> 4; \
+ *_r2 = _eip[1] & 0xf; \
+ return 1; \
+ } \
+ return 0; \
+ } \
+ \
+ /* Decode RX instruction format. */ \
+ static inline int _is_rx (unsigned char *_eip, \
+ unsigned char _op, \
+ int *_r1, int *_d2, int *_x2, int *_b2) \
+ { \
+ if (_eip[0] == _op) \
+ { \
+ *_r1 = _eip[1] >> 4; \
+ *_x2 = _eip[1] & 0xf; \
+ *_b2 = _eip[2] >> 4; \
+ *_d2 = ((_eip[2] & 0xf) << 8) + _eip[3]; \
+ return 1; \
+ } \
+ return 0; \
+ } \
+ \
+ /* Decode RRE instruction format. */ \
+ static inline int _is_rre (unsigned char *_eip, \
+ unsigned char _op1, unsigned char _op2,\
+ int *_r1, int *_r2) \
+ { \
+ if (_eip[0] == _op1 && _eip[1] == _op2) \
+ { \
+ *_r1 = _eip[3] >> 4; \
+ *_r2 = _eip[3] & 0xf; \
+ return 1; \
+ } \
+ return 0; \
+ } \
+ \
+ /* Decode RXY instruction format. */ \
+ static inline int _is_rxy (unsigned char *_eip, \
+ unsigned char _op1, unsigned char _op2,\
+ int *_r1, int *_d2, int *_x2, int *_b2)\
+ { \
+ if (_eip[0] == _op1 && _eip[5] == _op2) \
+ { \
+ *_r1 = _eip[1] >> 4; \
+ *_x2 = _eip[1] & 0xf; \
+ *_b2 = _eip[2] >> 4; \
+ *_d2 = ((_eip[2] & 0xf) << 8) + _eip[3] + (_eip[4] << 12); \
+ /* We have a 20-bit signed displacement. */ \
+ *_d2 = (*_d2 ^ 0x80000) - 0x80000; \
+ return 1; \
+ } \
+ return 0; \
+ } \
+ \
+ /* Compute effective address. */ \
+ static inline unsigned long _eff (unsigned long *_regs, \
+ long _d, int _x, int _b) \
+ { \
+ return _d + (_x? _regs[_x] : 0) + (_b? _regs[_b] : 0); \
+ } \
+ }; \
+ \
+ \
+ /* DR r1,r2 */ \
+ if (_decode::_is_rr (_eip, 0x1d, &_r1, &_r2) \
+ && (int) _regs[_r1] == -1 && (int) _regs[_r1+1] == INT_MIN \
+ && (int) _regs[_r2] == -1) \
+ { \
+ _regs[_r1] &= ~0xffffffff; \
+ return; \
+ } \
+ \
+ /* D r1,d2(x2,b2) */ \
+ if (_decode::_is_rx (_eip, 0x5d, &_r1, &_d2, &_x2, &_b2) \
+ && (int) _regs[_r1] == -1 && (int) _regs[_r1+1] == INT_MIN \
+ && *(int *) _decode::_eff (_regs, _d2, _x2, _b2) == -1) \
+ { \
+ _regs[_r1] &= ~0xffffffff; \
+ return; \
+ } \
+ \
+ /* DSGR r1,r2 */ \
+ if (_decode::_is_rre (_eip, 0xb9, 0x0d, &_r1, &_r2) \
+ && (long) _regs[_r1+1] == LONG_MIN \
+ && (long) _regs[_r2] == -1L) \
+ { \
+ _regs[_r1] = 0; \
+ return; \
+ } \
+ \
+ /* DSGFR r1,r2 */ \
+ if (_decode::_is_rre (_eip, 0xb9, 0x1d, &_r1, &_r2) \
+ && (long) _regs[_r1+1] == LONG_MIN \
+ && (int) _regs[_r2] == -1) \
+ { \
+ _regs[_r1] = 0; \
+ return; \
+ } \
+ \
+ /* DSG r1,d2(x2,b2) */ \
+ if (_decode::_is_rxy (_eip, 0xe3, 0x0d, &_r1, &_d2, &_x2, &_b2) \
+ && (long) _regs[_r1+1] == LONG_MIN \
+ && *(long *) _decode::_eff (_regs, _d2, _x2, _b2) == -1L) \
+ { \
+ _regs[_r1] = 0; \
+ return; \
+ } \
+ \
+ /* DSGF r1,d2(x2,b2) */ \
+ if (_decode::_is_rxy (_eip, 0xe3, 0x1d, &_r1, &_d2, &_x2, &_b2) \
+ && (long) _regs[_r1+1] == LONG_MIN \
+ && *(int *) _decode::_eff (_regs, _d2, _x2, _b2) == -1) \
+ { \
+ _regs[_r1] = 0; \
+ return; \
+ } \
+ \
+ } \
+ while (0)
+
/* For an explanation why we cannot simply use sigaction to
install the handlers, see i386-signal.h. */
*************** static void _name (int, siginfo_t *, voi
*** 36,42 ****
visible to us in a header file so we define it here. */
struct old_s390_kernel_sigaction {
! void (*k_sa_handler) (int, siginfo_t *, void *);
unsigned long k_sa_mask;
unsigned long k_sa_flags;
void (*sa_restorer) (void);
--- 188,194 ----
visible to us in a header file so we define it here. */
struct old_s390_kernel_sigaction {
! void (*k_sa_handler) (int, siginfo_t *, ucontext_t *);
unsigned long k_sa_mask;
unsigned long k_sa_flags;
void (*sa_restorer) (void);
--
Dr. Ulrich Weigand
weigand@informatik.uni-erlangen.de