Re: Update on SVE/sizeless types for C and C++

[Jim Wilson <jimw at sifive dot com>]

On Tue, Nov 12, 2019 at 8:06 AM Richard Sandiford
<richard.sandiford@arm.com> wrote:
> If the use of sizeless types does expand beyond SVE built-in types
> in future, the places that call the hook are the places that would
> need to deal directly with sizeless types.

We are using the same sizeless type infrastructure for the RISC-V
vector extension work.  The RVV extension is still in draft form and
still evolving.  The software is only in prototype form at the moment.
We don't have an ABI yet.  We have at least two competing proposals
for the intrinsics based programming model.  We don't have
auto-vectorization support yet.  Etc.  But SiFive has been working on
gcc patches for one of the intrinsics proposals, and EPI (European
Processor Initiative) has been working on llvm patches for another
intrinsics proposal, and both of these are using sizeless types.  RVV
has a similar design to ARM SVE where the size of types depends on the
hardware you are running on, and those sizes can change at run-time,
where they can be different from one loop iteration to the next.

Jim