Building IRA IR Pass 0 for finding pseudo/allocno costs r36: preferred X_REG, alternative NO_REGS, allocno X_REG a0 (r36,l0) best X_REG, allocno X_REG r35: preferred X_REG, alternative NO_REGS, allocno X_REG a10 (r35,l0) best X_REG, allocno X_REG r34: preferred X_REG, alternative NO_REGS, allocno X_REG a1 (r34,l0) best X_REG, allocno X_REG r33: preferred DATA_REGS, alternative NO_REGS, allocno DATA_REGS a11 (r33,l0) best DATA_REGS, allocno DATA_REGS r32: preferred DATA_REGS, alternative NO_REGS, allocno DATA_REGS a12 (r32,l0) best DATA_REGS, allocno DATA_REGS r31: preferred DATA_REGS, alternative NO_REGS, allocno DATA_REGS a14 (r31,l0) best DATA_REGS, allocno DATA_REGS r30: preferred NO_REGS, alternative NO_REGS, allocno NO_REGS a13 (r30,l0) best NO_REGS, allocno NO_REGS r29: preferred X_REG, alternative NO_REGS, allocno X_REG a15 (r29,l0) best X_REG, allocno X_REG r28: preferred X_REG, alternative NO_REGS, allocno X_REG a16 (r28,l0) best X_REG, allocno X_REG r27: preferred X_REG, alternative NO_REGS, allocno X_REG a17 (r27,l0) best X_REG, allocno X_REG r26: preferred DATA_REGS, alternative NO_REGS, allocno DATA_REGS a2 (r26,l0) best DATA_REGS, allocno DATA_REGS r25: preferred DATA_REGS, alternative NO_REGS, allocno DATA_REGS a4 (r25,l0) best DATA_REGS, allocno DATA_REGS r24: preferred DATA_REGS, alternative NO_REGS, allocno DATA_REGS a3 (r24,l0) best DATA_REGS, allocno DATA_REGS r23: preferred DATA_REGS, alternative NO_REGS, allocno DATA_REGS a5 (r23,l0) best DATA_REGS, allocno DATA_REGS r22: preferred DATA_REGS, alternative NO_REGS, allocno DATA_REGS a6 (r22,l0) best DATA_REGS, allocno DATA_REGS r21: preferred DATA_REGS, alternative NO_REGS, allocno DATA_REGS a8 (r21,l0) best DATA_REGS, allocno DATA_REGS r20: preferred DATA_REGS, alternative NO_REGS, allocno DATA_REGS a7 (r20,l0) best DATA_REGS, allocno DATA_REGS r19: preferred DATA_REGS, alternative NO_REGS, allocno DATA_REGS a9 (r19,l0) best DATA_REGS, allocno DATA_REGS a0(r36,l0) costs: X_REG:0 MEM:5000 a1(r34,l0) costs: X_REG:0 MEM:84000 a2(r26,l0) costs: DATA_REGS:0 MEM:5000 a3(r24,l0) costs: DATA_REGS:0 MEM:5000 a4(r25,l0) costs: DATA_REGS:0 MEM:5000 a5(r23,l0) costs: DATA_REGS:0 MEM:5000 a6(r22,l0) costs: DATA_REGS:0 MEM:5000 a7(r20,l0) costs: DATA_REGS:0 MEM:5000 a8(r21,l0) costs: DATA_REGS:0 MEM:5000 a9(r19,l0) costs: DATA_REGS:0 MEM:5000 a10(r35,l0) costs: X_REG:0 MEM:5000 a11(r33,l0) costs: DATA_REGS:0 MEM:8000 a12(r32,l0) costs: DATA_REGS:0 MEM:7000 a13(r30,l0) costs: MEM:8000 a14(r31,l0) costs: DATA_REGS:0 MEM:7000 a15(r29,l0) costs: X_REG:0 MEM:8000 a16(r28,l0) costs: X_REG:0 MEM:8000 a17(r27,l0) costs: X_REG:2000 MEM:8000 Insn 43(l0): point = 0 Insn 39(l0): point = 3 Insn 38(l0): point = 5 Insn 37(l0): point = 7 Insn 36(l0): point = 9 Insn 35(l0): point = 11 Insn 34(l0): point = 13 Insn 33(l0): point = 15 Insn 32(l0): point = 17 Insn 31(l0): point = 19 Insn 30(l0): point = 21 Insn 29(l0): point = 23 Insn 28(l0): point = 25 Insn 27(l0): point = 27 Insn 26(l0): point = 29 Insn 25(l0): point = 31 Insn 24(l0): point = 33 Insn 23(l0): point = 35 Insn 22(l0): point = 37 Insn 21(l0): point = 39 Insn 20(l0): point = 41 Insn 19(l0): point = 43 Insn 18(l0): point = 45 Insn 17(l0): point = 47 Insn 16(l0): point = 49 Insn 15(l0): point = 51 Insn 14(l0): point = 53 Insn 9(l0): point = 55 Insn 8(l0): point = 57 Insn 7(l0): point = 59 Insn 6(l0): point = 61 Insn 5(l0): point = 63 Insn 4(l0): point = 65 Insn 3(l0): point = 67 Insn 2(l0): point = 69 Insn 10(l0): point = 71 a0(r36): [4..5] a1(r34): [4..55] a2(r26): [18..21] a3(r24): [20..25] a4(r25): [22..23] a5(r23): [26..27] a6(r22): [38..41] a7(r20): [40..45] a8(r21): [42..43] a9(r19): [46..47] a10(r35): [50..51] a11(r33): [56..57] a12(r32): [58..59] a13(r30): [60..61] a14(r31): [62..63] a15(r29): [64..65] a16(r28): [66..67] a17(r27): [68..69] Compressing live ranges: from 74 to 30 - 40% Ranges after the compression: a0(r36): [0..1] a1(r34): [0..15] a2(r26): [2..3] a3(r24): [2..5] a4(r25): [4..5] a5(r23): [6..7] a6(r22): [8..9] a7(r20): [8..11] a8(r21): [10..11] a9(r19): [12..13] a10(r35): [14..15] a11(r33): [16..17] a12(r32): [18..19] a13(r30): [20..21] a14(r31): [22..23] a15(r29): [24..25] a16(r28): [26..27] a17(r27): [28..29] regions=1, blocks=4, points=30 allocnos=18 (big 0), copies=0, conflicts=0, ranges=18 Disposition: 9:r19 l0 6 7:r20 l0 7 8:r21 l0 6 6:r22 l0 6 5:r23 l0 6 3:r24 l0 7 4:r25 l0 6 2:r26 l0 6 17:r27 l0 8 16:r28 l0 8 15:r29 l0 8 13:r30 l0 mem 14:r31 l0 6 12:r32 l0 6 11:r33 l0 6 1:r34 l0 mem 10:r35 l0 8 0:r36 l0 8 +++Costs: overall 94000, reg 2000, mem 92000, ld 0, st 0, move 0 +++ move loops 0, new jumps 0 ********** Local #1: ********** Spilling non-eliminable hard regs: 9 0 Non-pseudo reload: reject+=2 0 Non input pseudo reload: reject++ alt=0: Bad operand -- refuse alt=1: Bad operand -- refuse alt=2: Bad operand -- refuse 0 Non-pseudo reload: reject+=2 0 Non input pseudo reload: reject++ alt=3: Bad operand -- refuse 0 Non-pseudo reload: reject+=2 0 Non input pseudo reload: reject++ Cycle danger: overall += LRA_MAX_REJECT alt=4,overall=609,losers=1,rld_nregs=1 1 Non-pseudo reload: reject+=2 1 Spill pseudo into memory: reject+=3 Using memory insn operand 1: reject+=3 alt=5,overall=14,losers=1,rld_nregs=0 0 Non-pseudo reload: reject+=2 0 Non input pseudo reload: reject++ 1 Non-pseudo reload: reject+=2 1 Spill pseudo into memory: reject+=3 Using memory insn operand 1: reject+=3 alt=6,overall=23,losers=2 -- refuse alt=7,overall=0,losers=0,rld_nregs=0 Choosing alt 7 in insn 10: (0) m (1) Q {movpsi} alt=0,overall=0,losers=0,rld_nregs=0 1 Non-pseudo reload: reject+=2 1 Non input pseudo reload: reject++ alt=0,overall=9,losers=1 -- refuse Choosing alt 0 in insn 3: (0) =Q (1) %Q (2) n {addpsi3} alt=0,overall=0,losers=0,rld_nregs=0 1 Non-pseudo reload: reject+=2 1 Non input pseudo reload: reject++ alt=0,overall=9,losers=1 -- refuse Choosing alt 0 in insn 4: (0) =Q (1) %Q (2) n {addpsi3} alt=0,overall=0,losers=0,rld_nregs=0 Choosing alt 0 in insn 5: (0) =Q (1) B {zero_extendpsisi2} 0 Non input pseudo reload: reject++ alt=0,overall=7,losers=1,rld_nregs=1 0 Non input pseudo reload: reject++ alt=1,overall=7,losers=1,rld_nregs=1 Choosing alt 0 in insn 6: (0) =D (1) mr (2) i {lshrsi3} Creating newreg=37 from oldreg=30, assigning class DATA_REGS to r37 6: r37:SI=r31:SI 0>>0x3 REG_DEAD r31:SI REG_EQUAL udiv(r31:SI,0x8) Inserting insn reload after: 45: r30:SI=r37:SI 0 Non input pseudo reload: reject++ alt=0: Bad operand -- refuse 0 Non pseudo reload: reject++ alt=1: Bad operand -- refuse 0 Non pseudo reload: reject++ alt=2: Bad operand -- refuse 0 Non input pseudo reload: reject++ alt=3: Bad operand -- refuse 0 Non input pseudo reload: reject++ 1 Non pseudo reload: reject++ Cycle danger: overall += LRA_MAX_REJECT alt=4,overall=608,losers=1,rld_nregs=1 0 Non pseudo reload: reject++ Using memory insn operand 1: reject+=3 Cycle danger: overall += LRA_MAX_REJECT alt=5,overall=610,losers=1,rld_nregs=0 0 Non input pseudo reload: reject++ Using memory insn operand 1: reject+=3 Cycle danger: overall += LRA_MAX_REJECT alt=6,overall=616,losers=2,rld_nregs=1 0 Non pseudo reload: reject++ 1 Non pseudo reload: reject++ alt=7,overall=2,losers=0,rld_nregs=0 Choosing alt 7 in insn 45: (0) m (1) r {*movsi} 1 Small class reload: reject+=3 alt=0,overall=9,losers=1,rld_nregs=1 Choosing alt 0 in insn 7: (0) =Q (1) B {zero_extendpsisi2} Creating newreg=38, assigning class BASE_REGS to r38 7: r32:SI=zero_extend(r38:PSI) REG_DEAD r30:SI Inserting insn reload before: 46: r38:PSI=r30:SI#0 0 Non pseudo reload: reject++ alt=0: Bad operand -- refuse Using memory insn operand 0: reject+=3 0 Non input pseudo reload: reject++ alt=1: Bad operand -- refuse Using memory insn operand 0: reject+=3 0 Non input pseudo reload: reject++ alt=2: Bad operand -- refuse 0 Non pseudo reload: reject++ alt=3: Bad operand -- refuse 0 Non pseudo reload: reject++ Cycle danger: overall += LRA_MAX_REJECT alt=4,overall=607,losers=1,rld_nregs=1 Using memory insn operand 0: reject+=3 0 Non input pseudo reload: reject++ 1 Non pseudo reload: reject++ Cycle danger: overall += LRA_MAX_REJECT alt=5,overall=611,losers=1,rld_nregs=0 0 Non pseudo reload: reject++ 1 Non pseudo reload: reject++ alt=6,overall=2,losers=0,rld_nregs=0 Choosing alt 6 in insn 46: (0) Q (1) m {movpsi} alt=0,overall=0,losers=0,rld_nregs=0 Choosing alt 0 in insn 8: (0) =D (1) mr (2) i {ashlsi3} 0 Non input pseudo reload: reject++ alt=0,overall=7,losers=1,rld_nregs=1 Choosing alt 0 in insn 9: (0) =Q (1) Q {truncsipsi2} Creating newreg=39 from oldreg=34, assigning class ALL_REGS to r39 9: r39:PSI=trunc(r33:SI) REG_DEAD r33:SI Inserting insn reload after: 47: r34:PSI=r39:PSI 0 Non input pseudo reload: reject++ alt=0: Bad operand -- refuse 0 Non pseudo reload: reject++ alt=1: Bad operand -- refuse 0 Non pseudo reload: reject++ alt=2: Bad operand -- refuse 0 Non input pseudo reload: reject++ alt=3: Bad operand -- refuse 0 Non input pseudo reload: reject++ 1 Non pseudo reload: reject++ 1 Non pseudo costly reload: reject++ Cycle danger: overall += LRA_MAX_REJECT alt=4,overall=609,losers=1,rld_nregs=1 0 Non pseudo reload: reject++ Using memory insn operand 1: reject+=3 Cycle danger: overall += LRA_MAX_REJECT alt=5,overall=610,losers=1,rld_nregs=0 0 Non input pseudo reload: reject++ Using memory insn operand 1: reject+=3 Cycle danger: overall += LRA_MAX_REJECT alt=6,overall=616,losers=2,rld_nregs=1 0 Non pseudo reload: reject++ 1 Non pseudo reload: reject++ 1 Non pseudo costly reload: reject++ alt=7,overall=3,losers=0,rld_nregs=0 Choosing alt 7 in insn 47: (0) m (1) Q {movpsi} Creating newreg=40 from oldreg=34, assigning class GENERAL_REGS to address r40 Creating newreg=41, assigning class GENERAL_REGS to address r41 0 Non-pseudo reload: reject+=2 0 Non input pseudo reload: reject++ alt=0: Bad operand -- refuse alt=1: Bad operand -- refuse alt=2: Bad operand -- refuse 0 Non-pseudo reload: reject+=2 0 Non input pseudo reload: reject++ alt=3: Bad operand -- refuse 0 Non-pseudo reload: reject+=2 0 Non input pseudo reload: reject++ 1 Non-pseudo reload: reject+=2 1 Non input pseudo reload: reject++ alt=4,overall=18,losers=2,rld_nregs=2 alt=5,overall=0,losers=0,rld_nregs=0 Choosing alt 5 in insn 14: (0) m (1) m {*movsi} 14: [r40:PSI+0x20]=[r41:PSI] Inserting insn reload before: 48: r40:PSI=r34:PSI 49: r41:PSI=[y:PSI+0x2f] 0 Non pseudo reload: reject++ alt=0: Bad operand -- refuse Using memory insn operand 0: reject+=3 0 Non input pseudo reload: reject++ alt=1: Bad operand -- refuse Using memory insn operand 0: reject+=3 0 Non input pseudo reload: reject++ alt=2: Bad operand -- refuse 0 Non pseudo reload: reject++ alt=3: Bad operand -- refuse 0 Non pseudo reload: reject++ Cycle danger: overall += LRA_MAX_REJECT alt=4,overall=607,losers=1,rld_nregs=1 Using memory insn operand 0: reject+=3 0 Non input pseudo reload: reject++ 1 Non pseudo reload: reject++ Cycle danger: overall += LRA_MAX_REJECT alt=5,overall=611,losers=1,rld_nregs=0 0 Non pseudo reload: reject++ 1 Non pseudo reload: reject++ alt=6,overall=2,losers=0,rld_nregs=0 Choosing alt 6 in insn 48: (0) Q (1) m {movpsi} 0 Non pseudo reload: reject++ alt=0: Bad operand -- refuse Using memory insn operand 0: reject+=3 0 Non input pseudo reload: reject++ alt=1: Bad operand -- refuse Using memory insn operand 0: reject+=3 0 Non input pseudo reload: reject++ alt=2: Bad operand -- refuse 0 Non pseudo reload: reject++ alt=3: Bad operand -- refuse 0 Non pseudo reload: reject++ 1 Non-pseudo reload: reject+=2 1 Non input pseudo reload: reject++ Cycle danger: overall += LRA_MAX_REJECT alt=4,overall=610,losers=1,rld_nregs=1 Using memory insn operand 0: reject+=3 0 Non input pseudo reload: reject++ alt=5,overall=10,losers=1,rld_nregs=0 0 Non pseudo reload: reject++ alt=6,overall=1,losers=0,rld_nregs=0 Choosing alt 6 in insn 49: (0) Q (1) m {movpsi} alt=0: Bad operand -- refuse 0 Spill pseudo into memory: reject+=3 Using memory insn operand 0: reject+=3 0 Non input pseudo reload: reject++ alt=1: Bad operand -- refuse 0 Spill pseudo into memory: reject+=3 Using memory insn operand 0: reject+=3 0 Non input pseudo reload: reject++ alt=2: Bad operand -- refuse alt=3: Bad operand -- refuse 1 Non-pseudo reload: reject+=2 1 Non input pseudo reload: reject++ Cycle danger: overall += LRA_MAX_REJECT alt=4,overall=609,losers=1,rld_nregs=1 0 Spill pseudo into memory: reject+=3 Using memory insn operand 0: reject+=3 0 Non input pseudo reload: reject++ alt=5,overall=13,losers=1,rld_nregs=0 alt=6,overall=0,losers=0,rld_nregs=0 Choosing alt 6 in insn 15: (0) Q (1) m {movpsi} Creating newreg=42 from oldreg=34, assigning class GENERAL_REGS to address r42 0 Non-pseudo reload: reject+=2 0 Non input pseudo reload: reject++ alt=0: Bad operand -- refuse alt=1: Bad operand -- refuse alt=2: Bad operand -- refuse 0 Non-pseudo reload: reject+=2 0 Non input pseudo reload: reject++ alt=3: Bad operand -- refuse 0 Non-pseudo reload: reject+=2 0 Non input pseudo reload: reject++ 1 Non-pseudo reload: reject+=2 1 Non input pseudo reload: reject++ alt=4,overall=18,losers=2,rld_nregs=2 alt=5,overall=0,losers=0,rld_nregs=0 Choosing alt 5 in insn 16: (0) m (1) m {*movsi} 16: [r42:PSI+0x24]=[r35:PSI+0x4] REG_DEAD r35:PSI Inserting insn reload before: 50: r42:PSI=r34:PSI 0 Non pseudo reload: reject++ alt=0: Bad operand -- refuse Using memory insn operand 0: reject+=3 0 Non input pseudo reload: reject++ alt=1: Bad operand -- refuse Using memory insn operand 0: reject+=3 0 Non input pseudo reload: reject++ alt=2: Bad operand -- refuse 0 Non pseudo reload: reject++ alt=3: Bad operand -- refuse 0 Non pseudo reload: reject++ Cycle danger: overall += LRA_MAX_REJECT alt=4,overall=607,losers=1,rld_nregs=1 Using memory insn operand 0: reject+=3 0 Non input pseudo reload: reject++ 1 Non pseudo reload: reject++ Cycle danger: overall += LRA_MAX_REJECT alt=5,overall=611,losers=1,rld_nregs=0 0 Non pseudo reload: reject++ 1 Non pseudo reload: reject++ alt=6,overall=2,losers=0,rld_nregs=0 Choosing alt 6 in insn 50: (0) Q (1) m {movpsi} Creating newreg=43 from oldreg=34, assigning class GENERAL_REGS to address r43 alt=0: Bad operand -- refuse 0 Spill pseudo into memory: reject+=3 Using memory insn operand 0: reject+=3 0 Non input pseudo reload: reject++ alt=1: Bad operand -- refuse 0 Spill pseudo into memory: reject+=3 Using memory insn operand 0: reject+=3 0 Non input pseudo reload: reject++ alt=2: Bad operand -- refuse alt=3: Bad operand -- refuse 1 Non-pseudo reload: reject+=2 1 Non input pseudo reload: reject++ Cycle danger: overall += LRA_MAX_REJECT alt=4,overall=609,losers=1,rld_nregs=1 0 Spill pseudo into memory: reject+=3 Using memory insn operand 0: reject+=3 0 Non input pseudo reload: reject++ alt=5,overall=13,losers=1,rld_nregs=0 alt=6,overall=0,losers=0,rld_nregs=0 Choosing alt 6 in insn 17: (0) r (1) m {*movsi} 17: r19:SI=[r43:PSI+0x20] Inserting insn reload before: 51: r43:PSI=r34:PSI 0 Non pseudo reload: reject++ alt=0: Bad operand -- refuse Using memory insn operand 0: reject+=3 0 Non input pseudo reload: reject++ alt=1: Bad operand -- refuse Using memory insn operand 0: reject+=3 0 Non input pseudo reload: reject++ alt=2: Bad operand -- refuse 0 Non pseudo reload: reject++ alt=3: Bad operand -- refuse 0 Non pseudo reload: reject++ Cycle danger: overall += LRA_MAX_REJECT alt=4,overall=607,losers=1,rld_nregs=1 Using memory insn operand 0: reject+=3 0 Non input pseudo reload: reject++ 1 Non pseudo reload: reject++ Cycle danger: overall += LRA_MAX_REJECT alt=5,overall=611,losers=1,rld_nregs=0 0 Non pseudo reload: reject++ 1 Non pseudo reload: reject++ alt=6,overall=2,losers=0,rld_nregs=0 Choosing alt 6 in insn 51: (0) Q (1) m {movpsi} alt=0,overall=6,losers=1,rld_nregs=1 2 Non-pseudo reload: reject+=2 2 Non input pseudo reload: reject++ alt=1,overall=15,losers=2 -- refuse 1 Matching alt: reject+=2 1 Non-pseudo reload: reject+=2 1 Non input pseudo reload: reject++ alt=0,overall=11,losers=1 -- refuse 1 Matching alt: reject+=2 1 Non-pseudo reload: reject+=2 1 Non input pseudo reload: reject++ alt=1,overall=11,losers=1 -- refuse Choosing alt 0 in insn 18: (0) =D (1) %0 (2) i {andsi3} Creating newreg=44 from oldreg=19, assigning class DATA_REGS to r44 18: r44:SI=r44:SI&0x10001 REG_DEAD r19:SI Inserting insn reload before: 52: r44:SI=r19:SI Inserting insn reload after: 53: r20:SI=r44:SI Creating newreg=45 from oldreg=34, assigning class GENERAL_REGS to address r45 alt=0: Bad operand -- refuse 0 Spill pseudo into memory: reject+=3 Using memory insn operand 0: reject+=3 0 Non input pseudo reload: reject++ alt=1: Bad operand -- refuse 0 Spill pseudo into memory: reject+=3 Using memory insn operand 0: reject+=3 0 Non input pseudo reload: reject++ alt=2: Bad operand -- refuse alt=3: Bad operand -- refuse 1 Non-pseudo reload: reject+=2 1 Non input pseudo reload: reject++ Cycle danger: overall += LRA_MAX_REJECT alt=4,overall=609,losers=1,rld_nregs=1 0 Spill pseudo into memory: reject+=3 Using memory insn operand 0: reject+=3 0 Non input pseudo reload: reject++ alt=5,overall=13,losers=1,rld_nregs=0 alt=6,overall=0,losers=0,rld_nregs=0 Choosing alt 6 in insn 19: (0) r (1) m {*movsi} 19: r21:SI=[r45:PSI+0x24] Inserting insn reload before: 54: r45:PSI=r34:PSI 0 Non pseudo reload: reject++ alt=0: Bad operand -- refuse Using memory insn operand 0: reject+=3 0 Non input pseudo reload: reject++ alt=1: Bad operand -- refuse Using memory insn operand 0: reject+=3 0 Non input pseudo reload: reject++ alt=2: Bad operand -- refuse 0 Non pseudo reload: reject++ alt=3: Bad operand -- refuse 0 Non pseudo reload: reject++ Cycle danger: overall += LRA_MAX_REJECT alt=4,overall=607,losers=1,rld_nregs=1 Using memory insn operand 0: reject+=3 0 Non input pseudo reload: reject++ 1 Non pseudo reload: reject++ Cycle danger: overall += LRA_MAX_REJECT alt=5,overall=611,losers=1,rld_nregs=0 0 Non pseudo reload: reject++ 1 Non pseudo reload: reject++ alt=6,overall=2,losers=0,rld_nregs=0 Choosing alt 6 in insn 54: (0) Q (1) m {movpsi} alt=0,overall=0,losers=0,rld_nregs=0 1 Matching alt: reject+=2 1 Non-pseudo reload: reject+=2 1 Non input pseudo reload: reject++ alt=0,overall=11,losers=1 -- refuse 1 Matching alt: reject+=2 1 Non-pseudo reload: reject+=2 1 Non input pseudo reload: reject++ alt=1,overall=11,losers=1 -- refuse Choosing alt 0 in insn 20: (0) =D (1) %0 (2) i {andsi3} 0 Non-pseudo reload: reject+=2 0 Non input pseudo reload: reject++ alt=0: Bad operand -- refuse alt=1: Bad operand -- refuse alt=2: Bad operand -- refuse 0 Non-pseudo reload: reject+=2 0 Non input pseudo reload: reject++ alt=3: Bad operand -- refuse 0 Non-pseudo reload: reject+=2 0 Non input pseudo reload: reject++ Cycle danger: overall += LRA_MAX_REJECT alt=4,overall=609,losers=1,rld_nregs=1 1 Spill pseudo into memory: reject+=3 Using memory insn operand 1: reject+=3 alt=5,overall=12,losers=1,rld_nregs=0 0 Non-pseudo reload: reject+=2 0 Non input pseudo reload: reject++ 1 Spill pseudo into memory: reject+=3 Using memory insn operand 1: reject+=3 alt=6,overall=21,losers=2 -- refuse alt=7,overall=0,losers=0,rld_nregs=0 Choosing alt 7 in insn 21: (0) m (1) r {*movsi} 0 Non-pseudo reload: reject+=2 0 Non input pseudo reload: reject++ alt=0: Bad operand -- refuse alt=1: Bad operand -- refuse alt=2: Bad operand -- refuse 0 Non-pseudo reload: reject+=2 0 Non input pseudo reload: reject++ alt=3: Bad operand -- refuse 0 Non-pseudo reload: reject+=2 0 Non input pseudo reload: reject++ Cycle danger: overall += LRA_MAX_REJECT alt=4,overall=609,losers=1,rld_nregs=1 1 Spill pseudo into memory: reject+=3 Using memory insn operand 1: reject+=3 alt=5,overall=12,losers=1,rld_nregs=0 0 Non-pseudo reload: reject+=2 0 Non input pseudo reload: reject++ 1 Spill pseudo into memory: reject+=3 Using memory insn operand 1: reject+=3 alt=6,overall=21,losers=2 -- refuse alt=7,overall=0,losers=0,rld_nregs=0 Choosing alt 7 in insn 22: (0) m (1) r {*movsi} Creating newreg=46 from oldreg=34, assigning class GENERAL_REGS to address r46 0 Non-pseudo reload: reject+=2 0 Non input pseudo reload: reject++ alt=0: Bad operand -- refuse alt=1: Bad operand -- refuse alt=2: Bad operand -- refuse 0 Non-pseudo reload: reject+=2 0 Non input pseudo reload: reject++ alt=3: Bad operand -- refuse 0 Non-pseudo reload: reject+=2 0 Non input pseudo reload: reject++ 1 Non-pseudo reload: reject+=2 1 Non input pseudo reload: reject++ alt=4,overall=18,losers=2,rld_nregs=2 alt=5,overall=0,losers=0,rld_nregs=0 Choosing alt 5 in insn 23: (0) m (1) m {*movsi} 23: [r46:PSI+0x8]=[y:PSI+0x33] Inserting insn reload before: 55: r46:PSI=r34:PSI 0 Non pseudo reload: reject++ alt=0: Bad operand -- refuse Using memory insn operand 0: reject+=3 0 Non input pseudo reload: reject++ alt=1: Bad operand -- refuse Using memory insn operand 0: reject+=3 0 Non input pseudo reload: reject++ alt=2: Bad operand -- refuse 0 Non pseudo reload: reject++ alt=3: Bad operand -- refuse 0 Non pseudo reload: reject++ Cycle danger: overall += LRA_MAX_REJECT alt=4,overall=607,losers=1,rld_nregs=1 Using memory insn operand 0: reject+=3 0 Non input pseudo reload: reject++ 1 Non pseudo reload: reject++ Cycle danger: overall += LRA_MAX_REJECT alt=5,overall=611,losers=1,rld_nregs=0 0 Non pseudo reload: reject++ 1 Non pseudo reload: reject++ alt=6,overall=2,losers=0,rld_nregs=0 Choosing alt 6 in insn 55: (0) Q (1) m {movpsi} Creating newreg=47 from oldreg=34, assigning class GENERAL_REGS to address r47 0 Non-pseudo reload: reject+=2 0 Non input pseudo reload: reject++ alt=0: Bad operand -- refuse alt=1: Bad operand -- refuse alt=2: Bad operand -- refuse 0 Non-pseudo reload: reject+=2 0 Non input pseudo reload: reject++ alt=3: Bad operand -- refuse 0 Non-pseudo reload: reject+=2 0 Non input pseudo reload: reject++ 1 Non-pseudo reload: reject+=2 1 Non input pseudo reload: reject++ alt=4,overall=18,losers=2,rld_nregs=2 alt=5,overall=0,losers=0,rld_nregs=0 Choosing alt 5 in insn 24: (0) m (1) m {*movsi} 24: [r47:PSI+0xc]=[y:PSI+0x37] Inserting insn reload before: 56: r47:PSI=r34:PSI 0 Non pseudo reload: reject++ alt=0: Bad operand -- refuse Using memory insn operand 0: reject+=3 0 Non input pseudo reload: reject++ alt=1: Bad operand -- refuse Using memory insn operand 0: reject+=3 0 Non input pseudo reload: reject++ alt=2: Bad operand -- refuse 0 Non pseudo reload: reject++ alt=3: Bad operand -- refuse 0 Non pseudo reload: reject++ Cycle danger: overall += LRA_MAX_REJECT alt=4,overall=607,losers=1,rld_nregs=1 Using memory insn operand 0: reject+=3 0 Non input pseudo reload: reject++ 1 Non pseudo reload: reject++ Cycle danger: overall += LRA_MAX_REJECT alt=5,overall=611,losers=1,rld_nregs=0 0 Non pseudo reload: reject++ 1 Non pseudo reload: reject++ alt=6,overall=2,losers=0,rld_nregs=0 Choosing alt 6 in insn 56: (0) Q (1) m {movpsi} Creating newreg=48 from oldreg=34, assigning class GENERAL_REGS to address r48 Reuse r48 for reload r34:PSI 0 Non-pseudo reload: reject+=2 0 Non input pseudo reload: reject++ alt=0: Bad operand -- refuse alt=1: Bad operand -- refuse alt=2: Bad operand -- refuse 0 Non-pseudo reload: reject+=2 0 Non input pseudo reload: reject++ alt=3: Bad operand -- refuse 0 Non-pseudo reload: reject+=2 0 Non input pseudo reload: reject++ 1 Non-pseudo reload: reject+=2 1 Non input pseudo reload: reject++ alt=4,overall=18,losers=2,rld_nregs=2 alt=5,overall=0,losers=0,rld_nregs=0 Choosing alt 5 in insn 25: (0) m (1) m {*movsi} 25: [r48:PSI+0x18]=[r48:PSI+0x8] Inserting insn reload before: 57: r48:PSI=r34:PSI 0 Non pseudo reload: reject++ alt=0: Bad operand -- refuse Using memory insn operand 0: reject+=3 0 Non input pseudo reload: reject++ alt=1: Bad operand -- refuse Using memory insn operand 0: reject+=3 0 Non input pseudo reload: reject++ alt=2: Bad operand -- refuse 0 Non pseudo reload: reject++ alt=3: Bad operand -- refuse 0 Non pseudo reload: reject++ Cycle danger: overall += LRA_MAX_REJECT alt=4,overall=607,losers=1,rld_nregs=1 Using memory insn operand 0: reject+=3 0 Non input pseudo reload: reject++ 1 Non pseudo reload: reject++ Cycle danger: overall += LRA_MAX_REJECT alt=5,overall=611,losers=1,rld_nregs=0 0 Non pseudo reload: reject++ 1 Non pseudo reload: reject++ alt=6,overall=2,losers=0,rld_nregs=0 Choosing alt 6 in insn 57: (0) Q (1) m {movpsi} Creating newreg=49 from oldreg=34, assigning class GENERAL_REGS to address r49 Reuse r49 for reload r34:PSI 0 Non-pseudo reload: reject+=2 0 Non input pseudo reload: reject++ alt=0: Bad operand -- refuse alt=1: Bad operand -- refuse alt=2: Bad operand -- refuse 0 Non-pseudo reload: reject+=2 0 Non input pseudo reload: reject++ alt=3: Bad operand -- refuse 0 Non-pseudo reload: reject+=2 0 Non input pseudo reload: reject++ 1 Non-pseudo reload: reject+=2 1 Non input pseudo reload: reject++ alt=4,overall=18,losers=2,rld_nregs=2 alt=5,overall=0,losers=0,rld_nregs=0 Choosing alt 5 in insn 26: (0) m (1) m {*movsi} 26: [r49:PSI+0x1c]=[r49:PSI+0xc] Inserting insn reload before: 58: r49:PSI=r34:PSI 0 Non pseudo reload: reject++ alt=0: Bad operand -- refuse Using memory insn operand 0: reject+=3 0 Non input pseudo reload: reject++ alt=1: Bad operand -- refuse Using memory insn operand 0: reject+=3 0 Non input pseudo reload: reject++ alt=2: Bad operand -- refuse 0 Non pseudo reload: reject++ alt=3: Bad operand -- refuse 0 Non pseudo reload: reject++ Cycle danger: overall += LRA_MAX_REJECT alt=4,overall=607,losers=1,rld_nregs=1 Using memory insn operand 0: reject+=3 0 Non input pseudo reload: reject++ 1 Non pseudo reload: reject++ Cycle danger: overall += LRA_MAX_REJECT alt=5,overall=611,losers=1,rld_nregs=0 0 Non pseudo reload: reject++ 1 Non pseudo reload: reject++ alt=6,overall=2,losers=0,rld_nregs=0 Choosing alt 6 in insn 58: (0) Q (1) m {movpsi} Creating newreg=50 from oldreg=34, assigning class GENERAL_REGS to address r50 alt=0: Bad operand -- refuse 0 Spill pseudo into memory: reject+=3 Using memory insn operand 0: reject+=3 0 Non input pseudo reload: reject++ alt=1: Bad operand -- refuse 0 Spill pseudo into memory: reject+=3 Using memory insn operand 0: reject+=3 0 Non input pseudo reload: reject++ alt=2: Bad operand -- refuse alt=3: Bad operand -- refuse 1 Non-pseudo reload: reject+=2 1 Non input pseudo reload: reject++ Cycle danger: overall += LRA_MAX_REJECT alt=4,overall=609,losers=1,rld_nregs=1 0 Spill pseudo into memory: reject+=3 Using memory insn operand 0: reject+=3 0 Non input pseudo reload: reject++ alt=5,overall=13,losers=1,rld_nregs=0 alt=6,overall=0,losers=0,rld_nregs=0 Choosing alt 6 in insn 27: (0) r (1) m {*movsi} 27: r23:SI=[r50:PSI+0x18] Inserting insn reload before: 59: r50:PSI=r34:PSI 0 Non pseudo reload: reject++ alt=0: Bad operand -- refuse Using memory insn operand 0: reject+=3 0 Non input pseudo reload: reject++ alt=1: Bad operand -- refuse Using memory insn operand 0: reject+=3 0 Non input pseudo reload: reject++ alt=2: Bad operand -- refuse 0 Non pseudo reload: reject++ alt=3: Bad operand -- refuse 0 Non pseudo reload: reject++ Cycle danger: overall += LRA_MAX_REJECT alt=4,overall=607,losers=1,rld_nregs=1 Using memory insn operand 0: reject+=3 0 Non input pseudo reload: reject++ 1 Non pseudo reload: reject++ Cycle danger: overall += LRA_MAX_REJECT alt=5,overall=611,losers=1,rld_nregs=0 0 Non pseudo reload: reject++ 1 Non pseudo reload: reject++ alt=6,overall=2,losers=0,rld_nregs=0 Choosing alt 6 in insn 59: (0) Q (1) m {movpsi} alt=0,overall=6,losers=1,rld_nregs=1 2 Non-pseudo reload: reject+=2 2 Non input pseudo reload: reject++ alt=1,overall=15,losers=2 -- refuse 1 Matching alt: reject+=2 1 Non-pseudo reload: reject+=2 1 Non input pseudo reload: reject++ alt=0,overall=11,losers=1 -- refuse 1 Matching alt: reject+=2 1 Non-pseudo reload: reject+=2 1 Non input pseudo reload: reject++ alt=1,overall=11,losers=1 -- refuse Choosing alt 0 in insn 28: (0) =D (1) %0 (2) i {xorsi3} Creating newreg=51 from oldreg=23, assigning class DATA_REGS to r51 28: r51:SI=r51:SI^0x10001 REG_DEAD r23:SI Inserting insn reload before: 60: r51:SI=r23:SI Inserting insn reload after: 61: r24:SI=r51:SI Creating newreg=52 from oldreg=34, assigning class GENERAL_REGS to address r52 alt=0: Bad operand -- refuse 0 Spill pseudo into memory: reject+=3 Using memory insn operand 0: reject+=3 0 Non input pseudo reload: reject++ alt=1: Bad operand -- refuse 0 Spill pseudo into memory: reject+=3 Using memory insn operand 0: reject+=3 0 Non input pseudo reload: reject++ alt=2: Bad operand -- refuse alt=3: Bad operand -- refuse 1 Non-pseudo reload: reject+=2 1 Non input pseudo reload: reject++ Cycle danger: overall += LRA_MAX_REJECT alt=4,overall=609,losers=1,rld_nregs=1 0 Spill pseudo into memory: reject+=3 Using memory insn operand 0: reject+=3 0 Non input pseudo reload: reject++ alt=5,overall=13,losers=1,rld_nregs=0 alt=6,overall=0,losers=0,rld_nregs=0 Choosing alt 6 in insn 29: (0) r (1) m {*movsi} 29: r25:SI=[r52:PSI+0x1c] Inserting insn reload before: 62: r52:PSI=r34:PSI 0 Non pseudo reload: reject++ alt=0: Bad operand -- refuse Using memory insn operand 0: reject+=3 0 Non input pseudo reload: reject++ alt=1: Bad operand -- refuse Using memory insn operand 0: reject+=3 0 Non input pseudo reload: reject++ alt=2: Bad operand -- refuse 0 Non pseudo reload: reject++ alt=3: Bad operand -- refuse 0 Non pseudo reload: reject++ Cycle danger: overall += LRA_MAX_REJECT alt=4,overall=607,losers=1,rld_nregs=1 Using memory insn operand 0: reject+=3 0 Non input pseudo reload: reject++ 1 Non pseudo reload: reject++ Cycle danger: overall += LRA_MAX_REJECT alt=5,overall=611,losers=1,rld_nregs=0 0 Non pseudo reload: reject++ 1 Non pseudo reload: reject++ alt=6,overall=2,losers=0,rld_nregs=0 Choosing alt 6 in insn 62: (0) Q (1) m {movpsi} alt=0,overall=0,losers=0,rld_nregs=0 1 Matching alt: reject+=2 1 Non-pseudo reload: reject+=2 1 Non input pseudo reload: reject++ alt=0,overall=11,losers=1 -- refuse 1 Matching alt: reject+=2 1 Non-pseudo reload: reject+=2 1 Non input pseudo reload: reject++ alt=1,overall=11,losers=1 -- refuse Choosing alt 0 in insn 30: (0) =D (1) %0 (2) i {xorsi3} 0 Non-pseudo reload: reject+=2 0 Non input pseudo reload: reject++ alt=0: Bad operand -- refuse alt=1: Bad operand -- refuse alt=2: Bad operand -- refuse 0 Non-pseudo reload: reject+=2 0 Non input pseudo reload: reject++ alt=3: Bad operand -- refuse 0 Non-pseudo reload: reject+=2 0 Non input pseudo reload: reject++ Cycle danger: overall += LRA_MAX_REJECT alt=4,overall=609,losers=1,rld_nregs=1 1 Spill pseudo into memory: reject+=3 Using memory insn operand 1: reject+=3 alt=5,overall=12,losers=1,rld_nregs=0 0 Non-pseudo reload: reject+=2 0 Non input pseudo reload: reject++ 1 Spill pseudo into memory: reject+=3 Using memory insn operand 1: reject+=3 alt=6,overall=21,losers=2 -- refuse alt=7,overall=0,losers=0,rld_nregs=0 Choosing alt 7 in insn 31: (0) m (1) r {*movsi} 0 Non-pseudo reload: reject+=2 0 Non input pseudo reload: reject++ alt=0: Bad operand -- refuse alt=1: Bad operand -- refuse alt=2: Bad operand -- refuse 0 Non-pseudo reload: reject+=2 0 Non input pseudo reload: reject++ alt=3: Bad operand -- refuse 0 Non-pseudo reload: reject+=2 0 Non input pseudo reload: reject++ Cycle danger: overall += LRA_MAX_REJECT alt=4,overall=609,losers=1,rld_nregs=1 1 Spill pseudo into memory: reject+=3 Using memory insn operand 1: reject+=3 alt=5,overall=12,losers=1,rld_nregs=0 0 Non-pseudo reload: reject+=2 0 Non input pseudo reload: reject++ 1 Spill pseudo into memory: reject+=3 Using memory insn operand 1: reject+=3 alt=6,overall=21,losers=2 -- refuse alt=7,overall=0,losers=0,rld_nregs=0 Choosing alt 7 in insn 32: (0) m (1) r {*movsi} Creating newreg=53 from oldreg=34, assigning class GENERAL_REGS to address r53 0 Non-pseudo reload: reject+=2 0 Non input pseudo reload: reject++ alt=0: Bad operand -- refuse alt=1: Bad operand -- refuse alt=2: Bad operand -- refuse 0 Non-pseudo reload: reject+=2 0 Non input pseudo reload: reject++ alt=3: Bad operand -- refuse 0 Non-pseudo reload: reject+=2 0 Non input pseudo reload: reject++ 1 Non-pseudo reload: reject+=2 1 Non input pseudo reload: reject++ alt=4,overall=18,losers=2,rld_nregs=2 alt=5,overall=0,losers=0,rld_nregs=0 Choosing alt 5 in insn 33: (0) m (1) m {*movsi} 33: [r53:PSI]=[y:PSI+0x33] Inserting insn reload before: 63: r53:PSI=r34:PSI 0 Non pseudo reload: reject++ alt=0: Bad operand -- refuse Using memory insn operand 0: reject+=3 0 Non input pseudo reload: reject++ alt=1: Bad operand -- refuse Using memory insn operand 0: reject+=3 0 Non input pseudo reload: reject++ alt=2: Bad operand -- refuse 0 Non pseudo reload: reject++ alt=3: Bad operand -- refuse 0 Non pseudo reload: reject++ Cycle danger: overall += LRA_MAX_REJECT alt=4,overall=607,losers=1,rld_nregs=1 Using memory insn operand 0: reject+=3 0 Non input pseudo reload: reject++ 1 Non pseudo reload: reject++ Cycle danger: overall += LRA_MAX_REJECT alt=5,overall=611,losers=1,rld_nregs=0 0 Non pseudo reload: reject++ 1 Non pseudo reload: reject++ alt=6,overall=2,losers=0,rld_nregs=0 Choosing alt 6 in insn 63: (0) Q (1) m {movpsi} Creating newreg=54 from oldreg=34, assigning class GENERAL_REGS to address r54 0 Non-pseudo reload: reject+=2 0 Non input pseudo reload: reject++ alt=0: Bad operand -- refuse alt=1: Bad operand -- refuse alt=2: Bad operand -- refuse 0 Non-pseudo reload: reject+=2 0 Non input pseudo reload: reject++ alt=3: Bad operand -- refuse 0 Non-pseudo reload: reject+=2 0 Non input pseudo reload: reject++ 1 Non-pseudo reload: reject+=2 1 Non input pseudo reload: reject++ alt=4,overall=18,losers=2,rld_nregs=2 alt=5,overall=0,losers=0,rld_nregs=0 Choosing alt 5 in insn 34: (0) m (1) m {*movsi} 34: [r54:PSI+0x4]=[y:PSI+0x37] Inserting insn reload before: 64: r54:PSI=r34:PSI 0 Non pseudo reload: reject++ alt=0: Bad operand -- refuse Using memory insn operand 0: reject+=3 0 Non input pseudo reload: reject++ alt=1: Bad operand -- refuse Using memory insn operand 0: reject+=3 0 Non input pseudo reload: reject++ alt=2: Bad operand -- refuse 0 Non pseudo reload: reject++ alt=3: Bad operand -- refuse 0 Non pseudo reload: reject++ Cycle danger: overall += LRA_MAX_REJECT alt=4,overall=607,losers=1,rld_nregs=1 Using memory insn operand 0: reject+=3 0 Non input pseudo reload: reject++ 1 Non pseudo reload: reject++ Cycle danger: overall += LRA_MAX_REJECT alt=5,overall=611,losers=1,rld_nregs=0 0 Non pseudo reload: reject++ 1 Non pseudo reload: reject++ alt=6,overall=2,losers=0,rld_nregs=0 Choosing alt 6 in insn 64: (0) Q (1) m {movpsi} Creating newreg=55 from oldreg=34, assigning class GENERAL_REGS to address r55 Reuse r55 for reload r34:PSI 0 Non-pseudo reload: reject+=2 0 Non input pseudo reload: reject++ alt=0: Bad operand -- refuse alt=1: Bad operand -- refuse alt=2: Bad operand -- refuse 0 Non-pseudo reload: reject+=2 0 Non input pseudo reload: reject++ alt=3: Bad operand -- refuse 0 Non-pseudo reload: reject+=2 0 Non input pseudo reload: reject++ 1 Non-pseudo reload: reject+=2 1 Non input pseudo reload: reject++ alt=4,overall=18,losers=2,rld_nregs=2 alt=5,overall=0,losers=0,rld_nregs=0 Choosing alt 5 in insn 35: (0) m (1) m {*movsi} 35: [r55:PSI+0x10]=[r55:PSI] Inserting insn reload before: 65: r55:PSI=r34:PSI 0 Non pseudo reload: reject++ alt=0: Bad operand -- refuse Using memory insn operand 0: reject+=3 0 Non input pseudo reload: reject++ alt=1: Bad operand -- refuse Using memory insn operand 0: reject+=3 0 Non input pseudo reload: reject++ alt=2: Bad operand -- refuse 0 Non pseudo reload: reject++ alt=3: Bad operand -- refuse 0 Non pseudo reload: reject++ Cycle danger: overall += LRA_MAX_REJECT alt=4,overall=607,losers=1,rld_nregs=1 Using memory insn operand 0: reject+=3 0 Non input pseudo reload: reject++ 1 Non pseudo reload: reject++ Cycle danger: overall += LRA_MAX_REJECT alt=5,overall=611,losers=1,rld_nregs=0 0 Non pseudo reload: reject++ 1 Non pseudo reload: reject++ alt=6,overall=2,losers=0,rld_nregs=0 Choosing alt 6 in insn 65: (0) Q (1) m {movpsi} Creating newreg=56 from oldreg=34, assigning class GENERAL_REGS to address r56 Reuse r56 for reload r34:PSI 0 Non-pseudo reload: reject+=2 0 Non input pseudo reload: reject++ alt=0: Bad operand -- refuse alt=1: Bad operand -- refuse alt=2: Bad operand -- refuse 0 Non-pseudo reload: reject+=2 0 Non input pseudo reload: reject++ alt=3: Bad operand -- refuse 0 Non-pseudo reload: reject+=2 0 Non input pseudo reload: reject++ 1 Non-pseudo reload: reject+=2 1 Non input pseudo reload: reject++ alt=4,overall=18,losers=2,rld_nregs=2 alt=5,overall=0,losers=0,rld_nregs=0 Choosing alt 5 in insn 36: (0) m (1) m {*movsi} 36: [r56:PSI+0x14]=[r56:PSI+0x4] Inserting insn reload before: 66: r56:PSI=r34:PSI 0 Non pseudo reload: reject++ alt=0: Bad operand -- refuse Using memory insn operand 0: reject+=3 0 Non input pseudo reload: reject++ alt=1: Bad operand -- refuse Using memory insn operand 0: reject+=3 0 Non input pseudo reload: reject++ alt=2: Bad operand -- refuse 0 Non pseudo reload: reject++ alt=3: Bad operand -- refuse 0 Non pseudo reload: reject++ Cycle danger: overall += LRA_MAX_REJECT alt=4,overall=607,losers=1,rld_nregs=1 Using memory insn operand 0: reject+=3 0 Non input pseudo reload: reject++ 1 Non pseudo reload: reject++ Cycle danger: overall += LRA_MAX_REJECT alt=5,overall=611,losers=1,rld_nregs=0 0 Non pseudo reload: reject++ 1 Non pseudo reload: reject++ alt=6,overall=2,losers=0,rld_nregs=0 Choosing alt 6 in insn 66: (0) Q (1) m {movpsi} Creating newreg=57, assigning class GENERAL_REGS to address r57 Creating newreg=58 from oldreg=34, assigning class GENERAL_REGS to address r58 0 Non-pseudo reload: reject+=2 0 Non input pseudo reload: reject++ alt=0: Bad operand -- refuse alt=1: Bad operand -- refuse alt=2: Bad operand -- refuse 0 Non-pseudo reload: reject+=2 0 Non input pseudo reload: reject++ alt=3: Bad operand -- refuse 0 Non-pseudo reload: reject+=2 0 Non input pseudo reload: reject++ 1 Non-pseudo reload: reject+=2 1 Non input pseudo reload: reject++ alt=4,overall=18,losers=2,rld_nregs=2 alt=5,overall=0,losers=0,rld_nregs=0 Choosing alt 5 in insn 37: (0) m (1) m {*movsi} 37: [r57:PSI]=[r58:PSI+0x10] Inserting insn reload before: 67: r57:PSI=[y:PSI+0x2f] 68: r58:PSI=r34:PSI 0 Non pseudo reload: reject++ alt=0: Bad operand -- refuse Using memory insn operand 0: reject+=3 0 Non input pseudo reload: reject++ alt=1: Bad operand -- refuse Using memory insn operand 0: reject+=3 0 Non input pseudo reload: reject++ alt=2: Bad operand -- refuse 0 Non pseudo reload: reject++ alt=3: Bad operand -- refuse 0 Non pseudo reload: reject++ 1 Non-pseudo reload: reject+=2 1 Non input pseudo reload: reject++ Cycle danger: overall += LRA_MAX_REJECT alt=4,overall=610,losers=1,rld_nregs=1 Using memory insn operand 0: reject+=3 0 Non input pseudo reload: reject++ alt=5,overall=10,losers=1,rld_nregs=0 0 Non pseudo reload: reject++ alt=6,overall=1,losers=0,rld_nregs=0 Choosing alt 6 in insn 67: (0) Q (1) m {movpsi} 0 Non pseudo reload: reject++ alt=0: Bad operand -- refuse Using memory insn operand 0: reject+=3 0 Non input pseudo reload: reject++ alt=1: Bad operand -- refuse Using memory insn operand 0: reject+=3 0 Non input pseudo reload: reject++ alt=2: Bad operand -- refuse 0 Non pseudo reload: reject++ alt=3: Bad operand -- refuse 0 Non pseudo reload: reject++ Cycle danger: overall += LRA_MAX_REJECT alt=4,overall=607,losers=1,rld_nregs=1 Using memory insn operand 0: reject+=3 0 Non input pseudo reload: reject++ 1 Non pseudo reload: reject++ Cycle danger: overall += LRA_MAX_REJECT alt=5,overall=611,losers=1,rld_nregs=0 0 Non pseudo reload: reject++ 1 Non pseudo reload: reject++ alt=6,overall=2,losers=0,rld_nregs=0 Choosing alt 6 in insn 68: (0) Q (1) m {movpsi} alt=0: Bad operand -- refuse 0 Spill pseudo into memory: reject+=3 Using memory insn operand 0: reject+=3 0 Non input pseudo reload: reject++ alt=1: Bad operand -- refuse 0 Spill pseudo into memory: reject+=3 Using memory insn operand 0: reject+=3 0 Non input pseudo reload: reject++ alt=2: Bad operand -- refuse alt=3: Bad operand -- refuse 1 Non-pseudo reload: reject+=2 1 Non input pseudo reload: reject++ Cycle danger: overall += LRA_MAX_REJECT alt=4,overall=609,losers=1,rld_nregs=1 0 Spill pseudo into memory: reject+=3 Using memory insn operand 0: reject+=3 0 Non input pseudo reload: reject++ alt=5,overall=13,losers=1,rld_nregs=0 alt=6,overall=0,losers=0,rld_nregs=0 Choosing alt 6 in insn 38: (0) Q (1) m {movpsi} Creating newreg=59 from oldreg=34, assigning class GENERAL_REGS to address r59 0 Non-pseudo reload: reject+=2 0 Non input pseudo reload: reject++ alt=0: Bad operand -- refuse alt=1: Bad operand -- refuse alt=2: Bad operand -- refuse 0 Non-pseudo reload: reject+=2 0 Non input pseudo reload: reject++ alt=3: Bad operand -- refuse 0 Non-pseudo reload: reject+=2 0 Non input pseudo reload: reject++ 1 Non-pseudo reload: reject+=2 1 Non input pseudo reload: reject++ alt=4,overall=18,losers=2,rld_nregs=2 alt=5,overall=0,losers=0,rld_nregs=0 Choosing alt 5 in insn 39: (0) m (1) m {*movsi} 39: [r36:PSI+0x4]=[r59:PSI+0x14] REG_DEAD r36:PSI REG_DEAD r34:PSI Inserting insn reload before: 69: r59:PSI=r34:PSI 0 Non pseudo reload: reject++ alt=0: Bad operand -- refuse Using memory insn operand 0: reject+=3 0 Non input pseudo reload: reject++ alt=1: Bad operand -- refuse Using memory insn operand 0: reject+=3 0 Non input pseudo reload: reject++ alt=2: Bad operand -- refuse 0 Non pseudo reload: reject++ alt=3: Bad operand -- refuse 0 Non pseudo reload: reject++ Cycle danger: overall += LRA_MAX_REJECT alt=4,overall=607,losers=1,rld_nregs=1 Using memory insn operand 0: reject+=3 0 Non input pseudo reload: reject++ 1 Non pseudo reload: reject++ Cycle danger: overall += LRA_MAX_REJECT alt=5,overall=611,losers=1,rld_nregs=0 0 Non pseudo reload: reject++ 1 Non pseudo reload: reject++ alt=6,overall=2,losers=0,rld_nregs=0 Choosing alt 6 in insn 69: (0) Q (1) m {movpsi} Spilling non-eliminable hard regs: 9 ********** Inheritance #1: ********** EBB 2 3 <<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<< Creating newreg=60 from oldreg=34, assigning class X_REG to inheritance r60 Original reg change 34->60 (bb2): 68: r58:PSI=r60:PSI Add inheritance<-original before: 70: r60:PSI=r34:PSI Inheritance reuse change 34->60 (bb2): 69: r59:PSI=r60:PSI >>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>> <<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<< Creating newreg=61 from oldreg=34, assigning class X_REG to inheritance r61 Original reg change 34->61 (bb2): 66: r56:PSI=r61:PSI Add inheritance<-original before: 71: r61:PSI=r34:PSI Inheritance reuse change 34->61 (bb2): 70: r60:PSI=r61:PSI >>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>> <<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<< Creating newreg=62 from oldreg=34, assigning class X_REG to inheritance r62 Original reg change 34->62 (bb2): 65: r55:PSI=r62:PSI Add inheritance<-original before: 72: r62:PSI=r34:PSI Inheritance reuse change 34->62 (bb2): 71: r61:PSI=r62:PSI >>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>> <<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<< Creating newreg=63 from oldreg=34, assigning class X_REG to inheritance r63 Original reg change 34->63 (bb2): 64: r54:PSI=r63:PSI Add inheritance<-original before: 73: r63:PSI=r34:PSI Inheritance reuse change 34->63 (bb2): 72: r62:PSI=r63:PSI >>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>> <<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<< Creating newreg=64 from oldreg=34, assigning class X_REG to inheritance r64 Original reg change 34->64 (bb2): 63: r53:PSI=r64:PSI Add inheritance<-original before: 74: r64:PSI=r34:PSI Inheritance reuse change 34->64 (bb2): 73: r63:PSI=r64:PSI >>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>> <<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<< Creating newreg=65 from oldreg=34, assigning class X_REG to inheritance r65 Original reg change 34->65 (bb2): 62: r52:PSI=r65:PSI Add inheritance<-original before: 75: r65:PSI=r34:PSI Inheritance reuse change 34->65 (bb2): 74: r64:PSI=r65:PSI >>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>> <<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<< Creating newreg=66 from oldreg=34, assigning class X_REG to inheritance r66 Original reg change 34->66 (bb2): 59: r50:PSI=r66:PSI Add inheritance<-original before: 76: r66:PSI=r34:PSI Inheritance reuse change 34->66 (bb2): 75: r65:PSI=r66:PSI >>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>> <<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<< Creating newreg=67 from oldreg=34, assigning class X_REG to inheritance r67 Original reg change 34->67 (bb2): 58: r49:PSI=r67:PSI Add inheritance<-original before: 77: r67:PSI=r34:PSI Inheritance reuse change 34->67 (bb2): 76: r66:PSI=r67:PSI >>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>> <<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<< Creating newreg=68 from oldreg=34, assigning class X_REG to inheritance r68 Original reg change 34->68 (bb2): 57: r48:PSI=r68:PSI Add inheritance<-original before: 78: r68:PSI=r34:PSI Inheritance reuse change 34->68 (bb2): 77: r67:PSI=r68:PSI >>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>> <<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<< Creating newreg=69 from oldreg=34, assigning class X_REG to inheritance r69 Original reg change 34->69 (bb2): 56: r47:PSI=r69:PSI Add inheritance<-original before: 79: r69:PSI=r34:PSI Inheritance reuse change 34->69 (bb2): 78: r68:PSI=r69:PSI >>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>> <<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<< Creating newreg=70 from oldreg=34, assigning class X_REG to inheritance r70 Original reg change 34->70 (bb2): 55: r46:PSI=r70:PSI Add inheritance<-original before: 80: r70:PSI=r34:PSI Inheritance reuse change 34->70 (bb2): 79: r69:PSI=r70:PSI >>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>> <<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<< Creating newreg=71 from oldreg=34, assigning class X_REG to inheritance r71 Original reg change 34->71 (bb2): 54: r45:PSI=r71:PSI Add inheritance<-original before: 81: r71:PSI=r34:PSI Inheritance reuse change 34->71 (bb2): 80: r70:PSI=r71:PSI >>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>> <<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<< Creating newreg=72 from oldreg=34, assigning class X_REG to inheritance r72 Original reg change 34->72 (bb2): 51: r43:PSI=r72:PSI Add inheritance<-original before: 82: r72:PSI=r34:PSI Inheritance reuse change 34->72 (bb2): 81: r71:PSI=r72:PSI >>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>> <<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<< Creating newreg=73 from oldreg=34, assigning class X_REG to inheritance r73 Original reg change 34->73 (bb2): 50: r42:PSI=r73:PSI Add inheritance<-original before: 83: r73:PSI=r34:PSI Inheritance reuse change 34->73 (bb2): 82: r72:PSI=r73:PSI >>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>> <<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<< Creating newreg=74 from oldreg=34, assigning class X_REG to inheritance r74 Original reg change 34->74 (bb2): 48: r40:PSI=r74:PSI Add inheritance<-original before: 84: r74:PSI=r34:PSI Inheritance reuse change 34->74 (bb2): 83: r73:PSI=r74:PSI >>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>> <<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<< Creating newreg=75 from oldreg=34, assigning class X_REG to inheritance r75 Original reg change 34->75 (bb2): 47: r75:PSI=r39:PSI Add original<-inheritance after: 85: r34:PSI=r75:PSI Inheritance reuse change 34->75 (bb2): 84: r74:PSI=r75:PSI >>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>> <<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<< Rejecting inheritance for 30 because of disjoint classes DATA_REGS and NO_REGS >>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>> Removing dead insn: 85: r34:PSI=r75:PSI ********** Pseudo live ranges #1: ********** BB 3 Insn 43: point = 0, n_alt = -1 BB 2 Insn 39: point = 0, n_alt = 5 Insn 69: point = 1, n_alt = 6 Creating copy r59<-r60@1000 Insn 38: point = 3, n_alt = 6 Insn 37: point = 4, n_alt = 5 Insn 68: point = 5, n_alt = 6 Creating copy r58<-r60@1000 Insn 70: point = 6, n_alt = -1 Creating copy r60<-r61@1000 Insn 67: point = 8, n_alt = 6 Insn 36: point = 9, n_alt = 5 Insn 66: point = 10, n_alt = 6 Creating copy r56<-r61@1000 Insn 71: point = 11, n_alt = -1 Creating copy r61<-r62@1000 Insn 35: point = 13, n_alt = 5 Insn 65: point = 14, n_alt = 6 Creating copy r55<-r62@1000 Insn 72: point = 15, n_alt = -1 Creating copy r62<-r63@1000 Insn 34: point = 17, n_alt = 5 Insn 64: point = 18, n_alt = 6 Creating copy r54<-r63@1000 Insn 73: point = 19, n_alt = -1 Creating copy r63<-r64@1000 Insn 33: point = 21, n_alt = 5 Insn 63: point = 22, n_alt = 6 Creating copy r53<-r64@1000 Insn 74: point = 23, n_alt = -1 Creating copy r64<-r65@1000 Insn 32: point = 25, n_alt = 7 Insn 31: point = 26, n_alt = 7 Insn 30: point = 27, n_alt = 0 Insn 29: point = 29, n_alt = 6 Insn 62: point = 31, n_alt = 6 Creating copy r52<-r65@1000 Insn 75: point = 32, n_alt = -1 Creating copy r65<-r66@1000 Insn 61: point = 34, n_alt = -2 Hard reg 7 is preferable by r51 with profit 1000 Insn 28: point = 36, n_alt = 0 Insn 60: point = 37, n_alt = -2 Hard reg 7 is preferable by r51 with profit 1000 Hard reg 6 is preferable by r51 with profit 1000 Insn 27: point = 39, n_alt = 6 Insn 59: point = 41, n_alt = 6 Creating copy r50<-r66@1000 Insn 76: point = 42, n_alt = -1 Creating copy r66<-r67@1000 Insn 26: point = 44, n_alt = 5 Insn 58: point = 45, n_alt = 6 Creating copy r49<-r67@1000 Insn 77: point = 46, n_alt = -1 Creating copy r67<-r68@1000 Insn 25: point = 48, n_alt = 5 Insn 57: point = 49, n_alt = 6 Creating copy r48<-r68@1000 Insn 78: point = 50, n_alt = -1 Creating copy r68<-r69@1000 Insn 24: point = 52, n_alt = 5 Insn 56: point = 53, n_alt = 6 Creating copy r47<-r69@1000 Insn 79: point = 54, n_alt = -1 Creating copy r69<-r70@1000 Insn 23: point = 56, n_alt = 5 Insn 55: point = 57, n_alt = 6 Creating copy r46<-r70@1000 Insn 80: point = 58, n_alt = -1 Creating copy r70<-r71@1000 Insn 22: point = 60, n_alt = 7 Insn 21: point = 61, n_alt = 7 Insn 20: point = 62, n_alt = 0 Insn 19: point = 64, n_alt = 6 Insn 54: point = 66, n_alt = 6 Creating copy r45<-r71@1000 Insn 81: point = 67, n_alt = -1 Creating copy r71<-r72@1000 Insn 53: point = 69, n_alt = -2 Hard reg 7 is preferable by r44 with profit 1000 Insn 18: point = 71, n_alt = 0 Insn 52: point = 72, n_alt = -2 Hard reg 7 is preferable by r44 with profit 1000 Hard reg 6 is preferable by r44 with profit 1000 Insn 17: point = 74, n_alt = 6 Insn 51: point = 76, n_alt = 6 Creating copy r43<-r72@1000 Insn 82: point = 77, n_alt = -1 Creating copy r72<-r73@1000 Insn 16: point = 79, n_alt = 5 Insn 50: point = 80, n_alt = 6 Creating copy r42<-r73@1000 Insn 83: point = 81, n_alt = -1 Creating copy r73<-r74@1000 Insn 15: point = 83, n_alt = 6 Insn 14: point = 84, n_alt = 5 Insn 49: point = 85, n_alt = 6 Insn 48: point = 86, n_alt = 6 Creating copy r40<-r74@1000 Insn 84: point = 87, n_alt = -1 Creating copy r74<-r75@1000 Insn 47: point = 89, n_alt = 7 Creating copy r39->r75@1000 Insn 9: point = 91, n_alt = 0 Insn 8: point = 93, n_alt = 0 Insn 7: point = 95, n_alt = 0 Insn 46: point = 97, n_alt = 6 Insn 45: point = 99, n_alt = 7 Insn 6: point = 101, n_alt = 0 Insn 5: point = 103, n_alt = 0 Insn 4: point = 105, n_alt = 0 Insn 3: point = 107, n_alt = 0 Insn 2: point = 109, n_alt = -2 Insn 10: point = 110, n_alt = 7 r19: [73..74] r20: [61..69] r21: [63..64] r22: [60..62] r23: [38..39] r24: [26..34] r25: [28..29] r26: [25..27] r27: [108..109] r28: [106..107] r29: [104..105] r30: [98..99] r31: [102..103] r32: [94..95] r33: [92..93] r35: [79..83] r36: [0..3] r37: [100..101] r38: [96..97] r39: [90..91] r40: [84..86] r41: [84..85] r42: [79..80] r43: [75..76] r44: [70..72] r45: [65..66] r46: [56..57] r47: [52..53] r48: [48..49] r49: [44..45] r50: [40..41] r51: [35..37] r52: [30..31] r53: [21..22] r54: [17..18] r55: [13..14] r56: [9..10] r57: [4..8] r58: [4..5] r59: [0..1] r60: [2..6] r61: [7..11] r62: [12..15] r63: [16..19] r64: [20..23] r65: [24..32] r66: [33..42] r67: [43..46] r68: [47..50] r69: [51..54] r70: [55..58] r71: [59..67] r72: [68..77] r73: [78..81] r74: [82..87] r75: [88..89] Compressing live ranges: from 110 to 80 - 72% Ranges after the compression: r19: [48..49] r20: [38..45] r21: [40..41] r22: [38..39] r23: [26..27] r24: [16..23] r25: [18..19] r26: [16..17] r27: [78..79] r28: [76..77] r29: [74..75] r30: [68..69] r31: [72..73] r32: [64..65] r33: [62..63] r35: [52..55] r36: [0..3] r37: [70..71] r38: [66..67] r39: [60..61] r40: [56..57] r41: [56..57] r42: [52..53] r43: [50..51] r44: [46..47] r45: [42..43] r46: [36..37] r47: [34..35] r48: [32..33] r49: [30..31] r50: [28..29] r51: [24..25] r52: [20..21] r53: [14..15] r54: [12..13] r55: [10..11] r56: [8..9] r57: [4..7] r58: [4..5] r59: [0..1] r60: [2..5] r61: [6..9] r62: [10..11] r63: [12..13] r64: [14..15] r65: [16..21] r66: [22..29] r67: [30..31] r68: [32..33] r69: [34..35] r70: [36..37] r71: [38..43] r72: [44..51] r73: [52..53] r74: [54..57] r75: [58..59] ********** Assignment #1: ********** Assigning to 66 (cl=X_REG, orig=34, freq=3000, tfirst=60, tfreq=17000)... Assign 8 to inheritance r66 (freq=3000) Hard reg 8 is preferable by r67 with profit 1000 Hard reg 8 is preferable by r68 with profit 500 Hard reg 8 is preferable by r69 with profit 250 Hard reg 8 is preferable by r70 with profit 125 Hard reg 8 is preferable by r71 with profit 62 Hard reg 8 is preferable by r72 with profit 31 Hard reg 8 is preferable by r45 with profit 31 Hard reg 8 is preferable by r46 with profit 62 Hard reg 8 is preferable by r47 with profit 125 Hard reg 8 is preferable by r48 with profit 250 Hard reg 8 is preferable by r49 with profit 500 Hard reg 8 is preferable by r50 with profit 1000 Hard reg 8 is preferable by r65 with profit 1000 Hard reg 8 is preferable by r52 with profit 500 Hard reg 8 is preferable by r64 with profit 500 Hard reg 8 is preferable by r53 with profit 250 Hard reg 8 is preferable by r63 with profit 250 Hard reg 8 is preferable by r54 with profit 125 Hard reg 8 is preferable by r62 with profit 125 Hard reg 8 is preferable by r55 with profit 62 Hard reg 8 is preferable by r61 with profit 62 Hard reg 8 is preferable by r56 with profit 31 Hard reg 8 is preferable by r60 with profit 31 Assigning to 72 (cl=X_REG, orig=34, freq=3000, tfirst=60, tfreq=17000)... Assign 8 to inheritance r72 (freq=3000) Hard reg 8 is preferable by r73 with profit 1000 Hard reg 8 is preferable by r74 with profit 500 Hard reg 8 is preferable by r75 with profit 250 Hard reg 8 is preferable by r39 with profit 125 Hard reg 8 is preferable by r40 with profit 250 Hard reg 8 is preferable by r42 with profit 500 Hard reg 8 is preferable by r43 with profit 1000 Hard reg 8 is preferable by r71 with profit 1062 Hard reg 8 is preferable by r45 with profit 531 Hard reg 8 is preferable by r70 with profit 625 Hard reg 8 is preferable by r46 with profit 312 Hard reg 8 is preferable by r69 with profit 500 Hard reg 8 is preferable by r47 with profit 250 Hard reg 8 is preferable by r68 with profit 625 Hard reg 8 is preferable by r48 with profit 312 Hard reg 8 is preferable by r67 with profit 1062 Hard reg 8 is preferable by r49 with profit 531 Assigning to 65 (cl=X_REG, orig=34, freq=3000, tfirst=60, tfreq=17000)... Assign 8 to inheritance r65 (freq=3000) Hard reg 8 is preferable by r52 with profit 1500 Hard reg 8 is preferable by r64 with profit 1500 Hard reg 8 is preferable by r53 with profit 750 Hard reg 8 is preferable by r63 with profit 750 Hard reg 8 is preferable by r54 with profit 375 Hard reg 8 is preferable by r62 with profit 375 Hard reg 8 is preferable by r55 with profit 187 Hard reg 8 is preferable by r61 with profit 187 Hard reg 8 is preferable by r56 with profit 93 Hard reg 8 is preferable by r60 with profit 93 Hard reg 8 is preferable by r58 with profit 31 Hard reg 8 is preferable by r59 with profit 31 Assigning to 71 (cl=X_REG, orig=34, freq=3000, tfirst=60, tfreq=17000)... Assign 8 to inheritance r71 (freq=3000) Hard reg 8 is preferable by r45 with profit 1531 Hard reg 8 is preferable by r70 with profit 1625 Hard reg 8 is preferable by r46 with profit 812 Hard reg 8 is preferable by r69 with profit 1000 Hard reg 8 is preferable by r47 with profit 500 Hard reg 8 is preferable by r68 with profit 875 Hard reg 8 is preferable by r48 with profit 437 Hard reg 8 is preferable by r67 with profit 1187 Hard reg 8 is preferable by r49 with profit 593 Assigning to 60 (cl=X_REG, orig=34, freq=3000, tfirst=60, tfreq=17000)... Assigning to 61 (cl=X_REG, orig=34, freq=3000, tfirst=60, tfreq=17000)... Assign 8 to inheritance r61 (freq=3000) Hard reg 8 is preferable by r62 with profit 1375 Hard reg 8 is preferable by r63 with profit 1250 Hard reg 8 is preferable by r64 with profit 1750 Hard reg 8 is preferable by r53 with profit 875 Hard reg 8 is preferable by r54 with profit 625 Hard reg 8 is preferable by r55 with profit 687 Hard reg 8 is preferable by r56 with profit 1093 Hard reg 8 is preferable by r60 with profit 1093 Hard reg 8 is preferable by r58 with profit 531 Hard reg 8 is preferable by r59 with profit 531 Assigning to 74 (cl=X_REG, orig=34, freq=3000, tfirst=60, tfreq=17000)... Assigning to 62 (cl=X_REG, orig=34, freq=3000, tfirst=60, tfreq=17000)... Assign 8 to inheritance r62 (freq=3000) Hard reg 8 is preferable by r63 with profit 2250 Hard reg 8 is preferable by r64 with profit 2250 Hard reg 8 is preferable by r53 with profit 1125 Hard reg 8 is preferable by r54 with profit 1125 Hard reg 8 is preferable by r55 with profit 1687 Assigning to 63 (cl=X_REG, orig=34, freq=3000, tfirst=60, tfreq=17000)... Assign 8 to inheritance r63 (freq=3000) Hard reg 8 is preferable by r64 with profit 3250 Hard reg 8 is preferable by r53 with profit 1625 Hard reg 8 is preferable by r54 with profit 2125 Assigning to 64 (cl=X_REG, orig=34, freq=3000, tfirst=60, tfreq=17000)... Assign 8 to inheritance r64 (freq=3000) Hard reg 8 is preferable by r53 with profit 2625 Assigning to 67 (cl=X_REG, orig=34, freq=3000, tfirst=60, tfreq=17000)... Assign 8 to inheritance r67 (freq=3000) Hard reg 8 is preferable by r68 with profit 1875 Hard reg 8 is preferable by r69 with profit 1500 Hard reg 8 is preferable by r70 with profit 1875 Hard reg 8 is preferable by r46 with profit 937 Hard reg 8 is preferable by r47 with profit 750 Hard reg 8 is preferable by r48 with profit 937 Hard reg 8 is preferable by r49 with profit 1593 Assigning to 68 (cl=X_REG, orig=34, freq=3000, tfirst=60, tfreq=17000)... Assign 8 to inheritance r68 (freq=3000) Hard reg 8 is preferable by r69 with profit 2500 Hard reg 8 is preferable by r70 with profit 2375 Hard reg 8 is preferable by r46 with profit 1187 Hard reg 8 is preferable by r47 with profit 1250 Hard reg 8 is preferable by r48 with profit 1937 Assigning to 69 (cl=X_REG, orig=34, freq=3000, tfirst=60, tfreq=17000)... Assign 8 to inheritance r69 (freq=3000) Hard reg 8 is preferable by r70 with profit 3375 Hard reg 8 is preferable by r46 with profit 1687 Hard reg 8 is preferable by r47 with profit 2250 Assigning to 70 (cl=X_REG, orig=34, freq=3000, tfirst=60, tfreq=17000)... Assign 8 to inheritance r70 (freq=3000) Hard reg 8 is preferable by r46 with profit 2687 Assigning to 73 (cl=X_REG, orig=34, freq=3000, tfirst=60, tfreq=17000)... Assigning to 75 (cl=X_REG, orig=34, freq=2000, tfirst=60, tfreq=17000)... Assign 8 to inheritance r75 (freq=2000) Hard reg 8 is preferable by r39 with profit 1125 Hard reg 8 is preferable by r74 with profit 1500 Hard reg 8 is preferable by r40 with profit 750 Hard reg 8 is preferable by r73 with profit 1500 Hard reg 8 is preferable by r42 with profit 750 Assigning to 38 (cl=BASE_REGS, orig=38, freq=2000, tfirst=38, tfreq=2000)... Assign 8 to reload r38 (freq=2000) Assigning to 44 (cl=DATA_REGS, orig=19, freq=3000, tfirst=44, tfreq=3000)... Assign 6 to reload r44 (freq=3000) Assigning to 51 (cl=DATA_REGS, orig=23, freq=3000, tfirst=51, tfreq=3000)... Assign 6 to reload r51 (freq=3000) Assigning to 37 (cl=DATA_REGS, orig=30, freq=2000, tfirst=37, tfreq=2000)... Assign 6 to reload r37 (freq=2000) Assigning to 39 (cl=ALL_REGS, orig=34, freq=2000, tfirst=39, tfreq=2000)... Assign 8 to reload r39 (freq=2000) Assigning to 40 (cl=GENERAL_REGS, orig=34, freq=2000, tfirst=40, tfreq=2000)... Assign 8 to reload r40 (freq=2000) Hard reg 8 is preferable by r74 with profit 2500 Hard reg 8 is preferable by r73 with profit 2000 Hard reg 8 is preferable by r42 with profit 1000 Assigning to 41 (cl=GENERAL_REGS, orig=41, freq=2000, tfirst=41, tfreq=2000)... Trying 0: Trying 1: Trying 2: Trying 3: Trying 4: Trying 5: Trying 6: Trying 7: Assigning to 42 (cl=GENERAL_REGS, orig=34, freq=2000, tfirst=42, tfreq=2000)... Trying 0: Trying 1: Trying 2: Trying 3: Trying 4: Trying 5: Trying 6: Trying 7: Assigning to 43 (cl=GENERAL_REGS, orig=34, freq=2000, tfirst=43, tfreq=2000)... Assign 8 to reload r43 (freq=2000) Assigning to 45 (cl=GENERAL_REGS, orig=34, freq=2000, tfirst=45, tfreq=2000)... Assign 8 to reload r45 (freq=2000) Assigning to 46 (cl=GENERAL_REGS, orig=34, freq=2000, tfirst=46, tfreq=2000)... Assign 8 to reload r46 (freq=2000) Assigning to 47 (cl=GENERAL_REGS, orig=34, freq=2000, tfirst=47, tfreq=2000)... Assign 8 to reload r47 (freq=2000) Assigning to 48 (cl=GENERAL_REGS, orig=34, freq=2000, tfirst=48, tfreq=2000)... Assign 8 to reload r48 (freq=2000) Assigning to 49 (cl=GENERAL_REGS, orig=34, freq=2000, tfirst=49, tfreq=2000)... Assign 8 to reload r49 (freq=2000) Assigning to 50 (cl=GENERAL_REGS, orig=34, freq=2000, tfirst=50, tfreq=2000)... Assign 8 to reload r50 (freq=2000) Assigning to 52 (cl=GENERAL_REGS, orig=34, freq=2000, tfirst=52, tfreq=2000)... Assign 8 to reload r52 (freq=2000) Assigning to 53 (cl=GENERAL_REGS, orig=34, freq=2000, tfirst=53, tfreq=2000)... Assign 8 to reload r53 (freq=2000) Assigning to 54 (cl=GENERAL_REGS, orig=34, freq=2000, tfirst=54, tfreq=2000)... Assign 8 to reload r54 (freq=2000) Assigning to 55 (cl=GENERAL_REGS, orig=34, freq=2000, tfirst=55, tfreq=2000)... Assign 8 to reload r55 (freq=2000) Assigning to 56 (cl=GENERAL_REGS, orig=34, freq=2000, tfirst=56, tfreq=2000)... Assign 8 to reload r56 (freq=2000) Assigning to 57 (cl=GENERAL_REGS, orig=57, freq=2000, tfirst=57, tfreq=2000)... Trying 0: Trying 1: Trying 2: Trying 3: Trying 4: Trying 5: Trying 6: Trying 7: Trying 8: spill 61(freq=3000) Now best 8(cost=2811, bad_spills=0, insn_pseudos=0) Spill inheritance r61(hr=8, freq=3000) for r57 Assign 8 to reload r57 (freq=2000) Assigning to 58 (cl=GENERAL_REGS, orig=34, freq=2000, tfirst=58, tfreq=2000)... Trying 0: Trying 1: Trying 2: Trying 3: Trying 4: Trying 5: Trying 6: Trying 7: Assigning to 59 (cl=GENERAL_REGS, orig=34, freq=2000, tfirst=59, tfreq=2000)... Trying 0: Trying 1: Trying 2: Trying 3: Trying 4: Trying 5: Trying 6: Trying 7: 2nd iter for reload pseudo assignments: Reload r41 assignment failure Reload r42 assignment failure Reload r58 assignment failure Reload r59 assignment failure Spill reload r40(hr=8, freq=2000) Spill r35(hr=8, freq=2000) Spill reload r57(hr=8, freq=2000) Spill r36(hr=8, freq=2000) Assigning to 74 (cl=X_REG, orig=34, freq=3000, tfirst=60, tfreq=17000)... Assign 8 to inheritance r74 (freq=3000) Hard reg 8 is preferable by r40 with profit 1750 Hard reg 8 is preferable by r73 with profit 3000 Hard reg 8 is preferable by r42 with profit 1500 Assigning to 73 (cl=X_REG, orig=34, freq=3000, tfirst=60, tfreq=17000)... Assign 8 to inheritance r73 (freq=3000) Hard reg 8 is preferable by r42 with profit 2500 Assigning to 40 (cl=GENERAL_REGS, orig=34, freq=2000, tfirst=40, tfreq=2000)... Assign 8 to reload r40 (freq=2000) Assigning to 41 (cl=GENERAL_REGS, orig=41, freq=2000, tfirst=41, tfreq=2000)... Trying 0: Trying 1: Trying 2: Trying 3: Trying 4: Trying 5: Trying 6: Trying 7: Assigning to 42 (cl=GENERAL_REGS, orig=34, freq=2000, tfirst=42, tfreq=2000)... Assign 8 to reload r42 (freq=2000) Assigning to 57 (cl=GENERAL_REGS, orig=57, freq=2000, tfirst=57, tfreq=2000)... Assign 8 to reload r57 (freq=2000) Assigning to 58 (cl=GENERAL_REGS, orig=34, freq=2000, tfirst=58, tfreq=2000)... Trying 0: Trying 1: Trying 2: Trying 3: Trying 4: Trying 5: Trying 6: Trying 7: Assigning to 59 (cl=GENERAL_REGS, orig=34, freq=2000, tfirst=59, tfreq=2000)... Assign 8 to reload r59 (freq=2000) Hard reg 8 is preferable by r60 with profit 2093 Hard reg 8 is preferable by r61 with profit 687 Hard reg 8 is preferable by r58 with profit 1031 Reassigning non-reload pseudos ********** Undoing inheritance #1: ********** Inherit 14 out of 16 (87.50%) Insn after restoring regs: 69: r59:PSI=r34:PSI REG_DEAD r34:PSI Insn after restoring regs: 68: r58:PSI=r34:PSI Removing inheritance: 70: r60:PSI=r61:PSI REG_DEAD r61:PSI Change reload insn: 66: r56:PSI=r62:PSI Insn after restoring regs: 71: r34:PSI=r62:PSI REG_DEAD r62:PSI ****** Splitting a hard reg after assignment #1: ****** Hard reg 8 is preferable by r60 with profit 2093 Hard reg 0 is preferable by r60 with profit 1000 Hard reg 8 is preferable by r61 with profit 687 Hard reg 0 is preferable by r61 with profit 500 /home/jmd/Source/GCC2/gcc/testsuite/gcc.c-torture/compile/pr53410-2.c: In function ‘f1’: /home/jmd/Source/GCC2/gcc/testsuite/gcc.c-torture/compile/pr53410-2.c:10:1: error: unable to find a register to spill /home/jmd/Source/GCC2/gcc/testsuite/gcc.c-torture/compile/pr53410-2.c:10:1: error: this is the insn: (insn 14 49 15 2 (set (mem:SI (plus:PSI (reg/f:PSI 40 [34]) (const_int 32 [0x20])) [2 S4 A64]) (mem:SI (reg:PSI 41) [2 *p_5(D)+0 S4 A8])) "/home/jmd/Source/GCC2/gcc/testsuite/gcc.c-torture/compile/pr53410-2.c":9:9 95 {*movsi} (expr_list:REG_DEAD (reg:PSI 41) (expr_list:REG_DEAD (reg/f:PSI 40 [34]) (nil)))) during RTL pass: reload /home/jmd/Source/GCC2/gcc/testsuite/gcc.c-torture/compile/pr53410-2.c:10:1: internal compiler error: in lra_split_hard_reg_for, at lra-assigns.c:1841 0x10f2889b _fatal_insn(char const*, rtx_def const*, char const*, int, char const*) /home/jmd/Source/GCC2/gcc/rtl-error.c:108 0x10c738ab lra_split_hard_reg_for() /home/jmd/Source/GCC2/gcc/lra-assigns.c:1841 0x10c68633 lra(_IO_FILE*) /home/jmd/Source/GCC2/gcc/lra.c:2555 0x10bcc9bb do_reload /home/jmd/Source/GCC2/gcc/ira.c:5522 0x10bcd187 execute /home/jmd/Source/GCC2/gcc/ira.c:5706 Please submit a full bug report, with preprocessed source if appropriate. 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