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Re: Expansion of narrowing math built-ins into power instructions


[ Please don't top-post ]

On Sun, Aug 25, 2019 at 07:32:01PM +0530, Tejas Joshi wrote:
> I want to extend this patch for FADDL and DADDL. What operand
> constraints should I use for TFmode alongside "f"?

It depends on the instruction you use, and what registers that then
works on.  GPRs get "r", FPRs get "f" for SFmode but "d" otherwise, the
VRs get "v", if all VSRs are allowed you get "wa".  And there are some
mode attributes to go with mode iterators for when you handle multiple
modes (which you always do, you need to handle KF as well).

What machine insns do you want to generate?  There most likely is
something a lot like it already, so take that as example?

> > In cases where long double and double have the same mode,
> >the daddl function should use the existing adddf3 pattern.

Sure, that probably should be handled in generic code (not rs6000).
Where it would generate an adddfdf2 it should just do an adddf3.

> So, should I use adddf3 for DADDL directly? How would I map the
> add<mode>3 optab with DADDL?

Simply check if source and target mode are the same?


Segher


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