This is the mail archive of the gcc@gcc.gnu.org mailing list for the GCC project.


Index Nav: [Date Index] [Subject Index] [Author Index] [Thread Index]
Message Nav: [Date Prev] [Date Next] [Thread Prev] [Thread Next]
Other format: [Raw text]

Re: Expansion of narrowing math built-ins into power instructions


Hi Tejas,

[ Please do not top-post. ]

On Thu, Aug 22, 2019 at 09:09:37AM +0530, Tejas Joshi wrote:
> Yes, I tried basically every combination I could think of, just not
> with the "isa attr". Now, I have the following code and it is still
> seems not to be working. Am I missing any options to pass?
> 
> (define_insn "add_truncdfsf3"
>   [(set (match_operand:SF 0 "gpc_reg_operand" "=f,wa")
>           (unspec:SF [(match_operand:DF 1 "gpc_reg_operand" "%d,wa")
>                              (match_operand:DF 2 "gpc_reg_operand" "d,wa")]
>                               UNSPEC_ADD_NARROWING))]
>   "TARGET_HARD_FLOAT"
>   "@
>    fadds %0,%1,%2
>    xsaddsp %x0,%x1,%x2"
>   [(set_attr "type" "fp")
>    (set_attr "isa" "*,p8v")])
> 
> with the code, I pass -O2 foo.c :
> float
> foo (double x, double y)
> {
>    return __builtin_fadd (x, y);
> }

What happens then?  "It does not work" is very very vague.  At least it
seems the compiler does build now?


Segher


Index Nav: [Date Index] [Subject Index] [Author Index] [Thread Index]
Message Nav: [Date Prev] [Date Next] [Thread Prev] [Thread Next]