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Re: Warning: unpredictable: identical transfer and status registers --`stxr w4,x5,[x4] using aarch64 poky gcc 8.3


OneWed, Feb 13, 2019 at 07:13:21AM +0000, Peng Fan wrote:
> We met an issue when building a piece jailhouse hypervisor code, "stxr   %w0, %3, %2\n\t" is 
> compiled as "stxr w4,x5,[x4]" which triggers the warning 
> "Warning: unpredictable: identical transfer and status registers"

This is not a GCC question.

The three registers, in order, are status, transfer, and base.  The warning
claims transfer and status are identical, but in fact base and status are.
The code (in binutils, gas/config/tc-aarch64.c) is

    case ldstexcl:
      /* It is unpredictable if the destination and status registers are the
         same.  */
      if ((aarch64_get_operand_class (opnds[0].type)
           == AARCH64_OPND_CLASS_INT_REG)
          && (aarch64_get_operand_class (opnds[1].type)
              == AARCH64_OPND_CLASS_INT_REG)
          && (opnds[0].reg.regno == opnds[1].reg.regno
              || opnds[0].reg.regno == opnds[2].reg.regno))
        as_warn (_("unpredictable: identical transfer and status registers"
                   " --`%s'"),
                 str);

so either that op0 == op2 test is spurious, or the warning message is
misleading.

Please ask on binutils@sourceware.org and/or file a bug at
https://sourceware.org/bugzilla/ ?


Segher


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