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New jump threading issue


Since the postreload_jump pass was added I'm having trouble with the AMD GCN port.

I have the following, after reload (RTL slightly simplified!):

(insn (set (reg scc) (gtu (reg s26) (reg s25))))
(jump_insn (set pc (if_then_else (ne scc 0)) (label_ref 46) pc)))
.....
(insn (set (reg scc) (eq (reg s18) (const_int 0))))
(jump_insn (set pc (if_then_else (ne scc 0)) (label_ref 56) pc))
(code_label 46)
(insn (set (reg scc) (ge s25 0)))
(jump_insn (set pc (if_then_else (ne scc 0)) (label_ref 48) pc)))
.....

and it's being transformed into this:

(insn (set (reg scc) (gtu (reg s26) (reg s25))))
(jump_insn (set pc (if_then_else (ne scc 0)) (label_ref 48) pc)))
.....
(insn (set (reg scc) (eq (reg s18) (const_int 0))))
(jump_insn (set pc (if_then_else (ne scc 0)) (label_ref 56) pc))
[2 insn deleted]
.....

So, basically, it seems to have decided that the final jump is always taken in one case, and never taken in the other, and I can't see any reason for either conclusion. s25 is an input parameter to the function.

It seems unlikely that the jump threading is that buggy, given it's an existing pass run again (right?), but I'm a bit confused about what I could be doing wrong here?

The affected function, udivsi3, is in libgcc, and every test case that calls it exits with the wrong output.

Any help appreciated. Full dumps attached.

Thanks

Andrew
;; Function __udivsi3 (__udivsi3, funcdef_no=3, decl_uid=1439, cgraph_uid=4, symbol_order=3)

      Creating newreg=467
Removing SCRATCH in insn #17 (nop 3)
rescanning insn with uid = 17.
      Creating newreg=468
Removing SCRATCH in insn #22 (nop 3)
rescanning insn with uid = 22.
      Creating newreg=469
Removing SCRATCH in insn #23 (nop 3)
rescanning insn with uid = 23.
      Creating newreg=470
Removing SCRATCH in insn #38 (nop 3)
rescanning insn with uid = 38.
      Creating newreg=471
Removing SCRATCH in insn #43 (nop 3)
rescanning insn with uid = 43.
      Creating newreg=472
Removing SCRATCH in insn #45 (nop 3)
rescanning insn with uid = 45.
      Creating newreg=473
Removing SCRATCH in insn #52 (nop 3)
rescanning insn with uid = 52.
      Creating newreg=474
Removing SCRATCH in insn #59 (nop 3)
rescanning insn with uid = 59.
      Creating newreg=475
Removing SCRATCH in insn #64 (nop 3)
rescanning insn with uid = 64.
      Creating newreg=476
Removing SCRATCH in insn #66 (nop 3)
      Creating newreg=477
Removing SCRATCH in insn #66 (nop 4)
rescanning insn with uid = 66.
      Creating newreg=478
Removing SCRATCH in insn #67 (nop 3)
rescanning insn with uid = 67.
      Creating newreg=479
Removing SCRATCH in insn #70 (nop 3)
rescanning insn with uid = 70.
      Creating newreg=480
Removing SCRATCH in insn #71 (nop 3)
rescanning insn with uid = 71.
      Creating newreg=481
Removing SCRATCH in insn #74 (nop 3)
rescanning insn with uid = 74.

********** Local #1: **********

	   Spilling non-eliminable hard regs: 16 17
New elimination table:
Can eliminate 416 to 16 (offset=-8, prev_offset=0)
Can eliminate 416 to 14 (offset=-8, prev_offset=0)
Can eliminate 418 to 16 (offset=0, prev_offset=0)
Can eliminate 418 to 14 (offset=0, prev_offset=0)
          alt=0,overall=0,losers=0,rld_nregs=0
	 Choosing alt 0 in insn 16:  (0) =cs  (2) SSA  (3) SSA {cstoresi4}
          alt=0,overall=0,losers=0,rld_nregs=0
	 Choosing alt 0 in insn 6:  (0) =SD  (1) SSA {*movsi_insn}
            3 Scratch win: reject+=2
          alt=0,overall=2,losers=0,rld_nregs=0
	 Choosing alt 0 in insn 17:  (2) ca  (3) =cs {cjump}
      Change to class SCC_CONDITIONAL_REG for r467
            3 Scratch win: reject+=2
          alt=0,overall=2,losers=0,rld_nregs=0
	 Choosing alt 0 in insn 22:  (0) =Sg  (1) SgB  (2) SgA  (3) =cs {ashlsi3}
      Change to class SCC_CONDITIONAL_REG for r468
            3 Scratch win: reject+=2
          alt=0,overall=2,losers=0,rld_nregs=0
	 Choosing alt 0 in insn 23:  (0) =Sg  (1) SgB  (2) SgA  (3) =cs {ashlsi3}
      Change to class SCC_CONDITIONAL_REG for r469
            0 Small class reload: reject+=3
            0 Non input pseudo reload: reject++
          alt=0,overall=10,losers=1,rld_nregs=1
            0 Small class reload: reject+=3
            0 Non input pseudo reload: reject++
          alt=1,overall=10,losers=1,rld_nregs=1
            0 Small class reload: reject+=3
            0 Non input pseudo reload: reject++
          alt=2,overall=10,losers=1,rld_nregs=1
            0 Small class reload: reject+=3
            0 Non input pseudo reload: reject++
          alt=3,overall=10,losers=1,rld_nregs=1
	 Choosing alt 0 in insn 24:  (0) =cs  (2) SSA  (3) SSA {cstoresi4}
      Creating newreg=482 from oldreg=442, assigning class SCC_CONDITIONAL_REG to r482
   24: r482:BI=gtu(r438:SI,r428:SI)
    Inserting insn reload after:
  111: r442:BI=r482:BI

            0 Small class reload: reject+=3
            0 Non input pseudo reload: reject++
          alt=0,overall=10,losers=1,rld_nregs=1
            0 Small class reload: reject+=3
            0 Non input pseudo reload: reject++
          alt=1,overall=10,losers=1,rld_nregs=1
            0 Small class reload: reject+=3
            0 Non input pseudo reload: reject++
            3 Non-pseudo reload: reject+=2
            3 Small class reload: reject+=3
            3 Non input pseudo reload: reject++
            alt=2,overall=22,losers=2 -- refuse
            0 Small class reload: reject+=3
            0 Non input pseudo reload: reject++
          alt=3,overall=10,losers=1,rld_nregs=1
	 Choosing alt 0 in insn 32:  (0) =cs  (2) SSA  (3) SSA {cstoresi4}
      Creating newreg=483 from oldreg=449, assigning class SCC_CONDITIONAL_REG to r483
   32: r483:BI=r429:SI!=0
    Inserting insn reload after:
  112: r449:BI=r483:BI

            3 Scratch win: reject+=2
          alt=0,overall=2,losers=0,rld_nregs=0
            3 Scratch win: reject+=2
          alt=0,overall=2,losers=0,rld_nregs=0
	 Choosing alt 0 in insn 38:  (0) =Sg  (1) %SgA  (2) SgB  (3) =cs {andsi3}
      Change to class SCC_CONDITIONAL_REG for r470
            3 Scratch win: reject+=2
          alt=0,overall=2,losers=0,rld_nregs=0
            3 Scratch win: reject+=2
          alt=0,overall=2,losers=0,rld_nregs=0
	 Choosing alt 0 in insn 43:  (0) =Sg  (1) %SgA  (2) SgB  (3) =cs {andsi3}
      Change to class SCC_CONDITIONAL_REG for r471
          alt=0,overall=0,losers=0,rld_nregs=0
	 Choosing alt 0 in insn 44:  (0) =cs  (2) SSA  (3) SSA {cstoresi4}
            3 Scratch win: reject+=2
          alt=0,overall=2,losers=0,rld_nregs=0
	 Choosing alt 0 in insn 45:  (2) ca  (3) =cs {cjump}
      Change to class SCC_CONDITIONAL_REG for r472
          alt=0,overall=0,losers=0,rld_nregs=0
	 Choosing alt 0 in insn 51:  (0) =cs  (2) SSA  (3) SSA {cstoresi4}
            3 Scratch win: reject+=2
          alt=0,overall=2,losers=0,rld_nregs=0
	 Choosing alt 0 in insn 52:  (2) ca  (3) =cs {cjump}
      Change to class SCC_CONDITIONAL_REG for r473
          alt=0,overall=0,losers=0,rld_nregs=0
	 Choosing alt 0 in insn 58:  (0) =cs  (2) SSA  (3) SSA {cstoresi4}
          alt=0,overall=0,losers=0,rld_nregs=0
	 Choosing alt 0 in insn 11:  (0) =SD  (1) SSA {*movsi_insn}
            3 Scratch win: reject+=2
          alt=0,overall=2,losers=0,rld_nregs=0
	 Choosing alt 0 in insn 59:  (2) ca  (3) =cs {cjump}
      Change to class SCC_CONDITIONAL_REG for r474
          alt=0,overall=0,losers=0,rld_nregs=0
	 Choosing alt 0 in insn 10:  (0) =SD  (1) SSA {*movsi_insn}
          alt=0,overall=0,losers=0,rld_nregs=0
	 Choosing alt 0 in insn 63:  (0) =cs  (2) SSA  (3) SSA {cstoresi4}
            3 Scratch win: reject+=2
          alt=0,overall=2,losers=0,rld_nregs=0
	 Choosing alt 0 in insn 64:  (2) ca  (3) =cs {cjump}
      Change to class SCC_CONDITIONAL_REG for r475
            3 Scratch win: reject+=2
          alt=0,overall=2,losers=0,rld_nregs=0
	 Choosing alt 0 in insn 66:  (0) =Sg  (1) SgA  (2) SgA  (3) =cs  (4) =X {subsi3}
      Change to class SCC_CONDITIONAL_REG for r476
      Change to class NO_REGS for r477
            3 Scratch win: reject+=2
          alt=0,overall=2,losers=0,rld_nregs=0
            3 Scratch win: reject+=2
          alt=0,overall=2,losers=0,rld_nregs=0
	 Choosing alt 0 in insn 67:  (0) =Sg  (1) %SgA  (2) SgB  (3) =cs {iorsi3}
      Change to class SCC_CONDITIONAL_REG for r478
            3 Scratch win: reject+=2
          alt=0,overall=2,losers=0,rld_nregs=0
	 Choosing alt 0 in insn 70:  (0) =Sg  (1) SgB  (2) SgA  (3) =cs {lshrsi3}
      Change to class SCC_CONDITIONAL_REG for r479
            3 Scratch win: reject+=2
          alt=0,overall=2,losers=0,rld_nregs=0
	 Choosing alt 0 in insn 71:  (0) =Sg  (1) SgB  (2) SgA  (3) =cs {lshrsi3}
      Change to class SCC_CONDITIONAL_REG for r480
          alt=0,overall=0,losers=0,rld_nregs=0
	 Choosing alt 0 in insn 73:  (0) =cs  (2) SSA  (3) SSA {cstoresi4}
            3 Scratch win: reject+=2
          alt=0,overall=2,losers=0,rld_nregs=0
	 Choosing alt 0 in insn 74:  (2) ca  (3) =cs {cjump}
      Change to class SCC_CONDITIONAL_REG for r481
	   Spilling non-eliminable hard regs: 16 17

********** Pseudo live ranges #1: **********

  BB 13
   Insn 84: point = 0, n_alt = -1
   Insn 83: point = 0, n_alt = -2
  BB 12
   Insn 76: point = 2, n_alt = -2
  BB 11
   Insn 74: point = 5, n_alt = 0
   Insn 73: point = 7, n_alt = 0
   Insn 71: point = 8, n_alt = 0
   Insn 70: point = 9, n_alt = 0
  BB 10
   Insn 67: point = 11, n_alt = 0
   Insn 66: point = 12, n_alt = 0
  BB 9
   Insn 64: point = 14, n_alt = 0
   Insn 63: point = 16, n_alt = 0
  BB 8
   Insn 10: point = 18, n_alt = 0
   Insn 9: point = 19, n_alt = -2
  BB 6
   Insn 107: point = 22, n_alt = -1
  BB 3
   Insn 104: point = 23, n_alt = -1
  BB 7
   Insn 59: point = 24, n_alt = 0
   Insn 109: point = 26, n_alt = -2
   Insn 11: point = 28, n_alt = 0
   Insn 58: point = 29, n_alt = 0
  BB 4
   Insn 45: point = 31, n_alt = 0
   Insn 44: point = 33, n_alt = 0
   Insn 43: point = 35, n_alt = 0
   Insn 38: point = 37, n_alt = 0
   Insn 112: point = 39, n_alt = -2
	Hard reg 18 is preferable by r483 with profit 893
   Insn 32: point = 41, n_alt = 0
   Insn 111: point = 42, n_alt = -2
	Hard reg 24 is preferable by r482 with profit 893
   Insn 24: point = 44, n_alt = 0
   Insn 23: point = 45, n_alt = 0
   Insn 22: point = 46, n_alt = 0
  BB 5
   Insn 52: point = 48, n_alt = 0
   Insn 51: point = 50, n_alt = 0
  BB 2
   Insn 17: point = 52, n_alt = 0
   Insn 6: point = 54, n_alt = 0
   Insn 5: point = 55, n_alt = -2
   Insn 16: point = 57, n_alt = 0
   Insn 3: point = 58, n_alt = -2
   Insn 102: point = 60, n_alt = -2
   Insn 2: point = 61, n_alt = -2
   Insn 101: point = 63, n_alt = -2
 r428: [5..55]
 r429: [5..54]
 r434: [5..19]
 r435: [3..18]
 r436: [24..28] [0..2]
 r438: [20..61]
 r439: [56..58]
 r440: [53..57]
 r442: [36..42]
 r449: [38..39]
 r454: [36..37]
 r457: [34..35]
 r458: [32..33]
 r459: [49..50]
 r460: [25..26]
 r461: [15..16]
 r462: [6..7]
 r464: [62..63]
 r465: [59..60]
 r466: [27..29]
 r467: [52..52]
 r468: [46..46]
 r469: [45..45]
 r470: [37..37]
 r471: [35..35]
 r472: [31..31]
 r473: [48..48]
 r474: [24..24]
 r475: [14..14]
 r476: [12..12]
 r477: [12..12]
 r478: [11..11]
 r479: [9..9]
 r480: [8..8]
 r481: [5..5]
 r482: [43..44]
 r483: [40..41]
Compressing live ranges: from 64 to 46 - 71%
Ranges after the compression:
 r428: [3..39]
 r429: [3..39]
 r434: [3..12]
 r435: [2..12]
 r436: [14..18] [0..1]
 r438: [13..43]
 r439: [40..41]
 r440: [38..41]
 r442: [24..29]
 r449: [26..27]
 r454: [24..25]
 r457: [22..23]
 r458: [20..21]
 r459: [35..36]
 r460: [15..16]
 r461: [11..12]
 r462: [4..5]
 r464: [44..45]
 r465: [42..43]
 r466: [17..18]
 r467: [37..37]
 r468: [33..33]
 r469: [32..32]
 r470: [25..25]
 r471: [23..23]
 r472: [19..19]
 r473: [34..34]
 r474: [14..14]
 r475: [10..10]
 r476: [9..9]
 r477: [9..9]
 r478: [8..8]
 r479: [7..7]
 r480: [6..6]
 r481: [3..3]
 r482: [30..31]
 r483: [28..29]

********** Inheritance #1: **********

EBB 2
EBB 3
EBB 4
EBB 5
EBB 6
EBB 7
EBB 8
EBB 9 10
EBB 11
EBB 12
EBB 13

********** Pseudo live ranges #2: **********

  BB 13
   Insn 84: point = 0, n_alt = -1
   Insn 83: point = 0, n_alt = -2
  BB 12
   Insn 76: point = 2, n_alt = -2
  BB 11
   Insn 74: point = 5, n_alt = 0
   Insn 73: point = 7, n_alt = 0
   Insn 71: point = 8, n_alt = 0
   Insn 70: point = 9, n_alt = 0
  BB 10
   Insn 67: point = 11, n_alt = 0
   Insn 66: point = 12, n_alt = 0
  BB 9
   Insn 64: point = 14, n_alt = 0
   Insn 63: point = 16, n_alt = 0
  BB 8
   Insn 10: point = 18, n_alt = 0
   Insn 9: point = 19, n_alt = -2
  BB 6
   Insn 107: point = 22, n_alt = -1
  BB 3
   Insn 104: point = 23, n_alt = -1
  BB 7
   Insn 59: point = 24, n_alt = 0
   Insn 109: point = 26, n_alt = -2
   Insn 11: point = 28, n_alt = 0
   Insn 58: point = 29, n_alt = 0
  BB 4
   Insn 45: point = 31, n_alt = 0
   Insn 44: point = 33, n_alt = 0
   Insn 43: point = 35, n_alt = 0
   Insn 38: point = 37, n_alt = 0
   Insn 112: point = 39, n_alt = -2
	Hard reg 18 is preferable by r483 with profit 893
   Insn 32: point = 41, n_alt = 0
   Insn 111: point = 42, n_alt = -2
	Hard reg 24 is preferable by r482 with profit 893
   Insn 24: point = 44, n_alt = 0
   Insn 23: point = 45, n_alt = 0
   Insn 22: point = 46, n_alt = 0
  BB 5
   Insn 52: point = 48, n_alt = 0
   Insn 51: point = 50, n_alt = 0
  BB 2
   Insn 17: point = 52, n_alt = 0
   Insn 6: point = 54, n_alt = 0
   Insn 5: point = 55, n_alt = -2
   Insn 16: point = 57, n_alt = 0
   Insn 3: point = 58, n_alt = -2
   Insn 102: point = 60, n_alt = -2
   Insn 2: point = 61, n_alt = -2
   Insn 101: point = 63, n_alt = -2
 r428: [5..55]
 r429: [5..54]
 r434: [5..19]
 r435: [3..18]
 r436: [24..28] [0..2]
 r438: [20..61]
 r439: [56..58]
 r440: [53..57]
 r442: [36..42]
 r449: [38..39]
 r454: [36..37]
 r457: [34..35]
 r458: [32..33]
 r459: [49..50]
 r460: [25..26]
 r461: [15..16]
 r462: [6..7]
 r464: [62..63]
 r465: [59..60]
 r466: [27..29]
 r467: [52..52]
 r468: [46..46]
 r469: [45..45]
 r470: [37..37]
 r471: [35..35]
 r472: [31..31]
 r473: [48..48]
 r474: [24..24]
 r475: [14..14]
 r476: [12..12]
 r477: [12..12]
 r478: [11..11]
 r479: [9..9]
 r480: [8..8]
 r481: [5..5]
 r482: [43..44]
 r483: [40..41]
Compressing live ranges: from 64 to 46 - 71%
Ranges after the compression:
 r428: [3..39]
 r429: [3..39]
 r434: [3..12]
 r435: [2..12]
 r436: [14..18] [0..1]
 r438: [13..43]
 r439: [40..41]
 r440: [38..41]
 r442: [24..29]
 r449: [26..27]
 r454: [24..25]
 r457: [22..23]
 r458: [20..21]
 r459: [35..36]
 r460: [15..16]
 r461: [11..12]
 r462: [4..5]
 r464: [44..45]
 r465: [42..43]
 r466: [17..18]
 r467: [37..37]
 r468: [33..33]
 r469: [32..32]
 r470: [25..25]
 r471: [23..23]
 r472: [19..19]
 r473: [34..34]
 r474: [14..14]
 r475: [10..10]
 r476: [9..9]
 r477: [9..9]
 r478: [8..8]
 r479: [7..7]
 r480: [6..6]
 r481: [3..3]
 r482: [30..31]
 r483: [28..29]

********** Assignment #1: **********

	 Assigning to 482 (cl=SCC_CONDITIONAL_REG, orig=442, freq=1786, tfirst=482, tfreq=1786)...
	   Assign 129 to reload r482 (freq=1786)
	 Assigning to 483 (cl=SCC_CONDITIONAL_REG, orig=449, freq=1786, tfirst=483, tfreq=1786)...
	   Assign 129 to reload r483 (freq=1786)
	 Assigning to 473 (cl=SCC_CONDITIONAL_REG, orig=473, freq=945, tfirst=473, tfreq=945)...
	   Assign 129 to reload r473 (freq=945)
	 Assigning to 468 (cl=SCC_CONDITIONAL_REG, orig=468, freq=893, tfirst=468, tfreq=893)...
	   Assign 129 to reload r468 (freq=893)
	 Assigning to 469 (cl=SCC_CONDITIONAL_REG, orig=469, freq=893, tfirst=469, tfreq=893)...
	   Assign 129 to reload r469 (freq=893)
	 Assigning to 470 (cl=SCC_CONDITIONAL_REG, orig=470, freq=893, tfirst=470, tfreq=893)...
	   Assign 129 to reload r470 (freq=893)
	 Assigning to 471 (cl=SCC_CONDITIONAL_REG, orig=471, freq=893, tfirst=471, tfreq=893)...
	   Assign 129 to reload r471 (freq=893)
	 Assigning to 472 (cl=SCC_CONDITIONAL_REG, orig=472, freq=893, tfirst=472, tfreq=893)...
	   Assign 129 to reload r472 (freq=893)
	 Assigning to 475 (cl=SCC_CONDITIONAL_REG, orig=475, freq=865, tfirst=475, tfreq=865)...
	   Assign 129 to reload r475 (freq=865)
	 Assigning to 479 (cl=SCC_CONDITIONAL_REG, orig=479, freq=865, tfirst=479, tfreq=865)...
	   Assign 129 to reload r479 (freq=865)
	 Assigning to 480 (cl=SCC_CONDITIONAL_REG, orig=480, freq=865, tfirst=480, tfreq=865)...
	   Assign 129 to reload r480 (freq=865)
	 Assigning to 481 (cl=SCC_CONDITIONAL_REG, orig=481, freq=865, tfirst=481, tfreq=865)...
	   Assign 129 to reload r481 (freq=865)
	 Assigning to 476 (cl=SCC_CONDITIONAL_REG, orig=476, freq=432, tfirst=476, tfreq=432)...
	   Assign 129 to reload r476 (freq=432)
	 Assigning to 478 (cl=SCC_CONDITIONAL_REG, orig=478, freq=432, tfirst=478, tfreq=432)...
	   Assign 129 to reload r478 (freq=432)
	 Assigning to 467 (cl=SCC_CONDITIONAL_REG, orig=467, freq=107, tfirst=467, tfreq=107)...
	   Assign 129 to reload r467 (freq=107)
	 Assigning to 474 (cl=SCC_CONDITIONAL_REG, orig=474, freq=49, tfirst=474, tfreq=49)...
	   Assign 129 to reload r474 (freq=49)

********** Undoing inheritance #1: **********


********** Local #2: **********

	   Spilling non-eliminable hard regs: 16 17
	   Spilling non-eliminable hard regs: 16 17
Restoring SCRATCH in insn #66(nop 4)
	   Spilling non-eliminable hard regs: 16 17
New elimination table:
Can eliminate 416 to 16 (offset=-8, prev_offset=-8)
Can eliminate 416 to 14 (offset=-8, prev_offset=0)
Can eliminate 418 to 16 (offset=0, prev_offset=0)
Can eliminate 418 to 14 (offset=0, prev_offset=0)
changing reg in insn 71
changing reg in insn 22
changing reg in insn 5
changing reg in insn 71
changing reg in insn 66
changing reg in insn 22
changing reg in insn 24
changing reg in insn 63
changing reg in insn 51
changing reg in insn 70
changing reg in insn 23
changing reg in insn 6
changing reg in insn 70
changing reg in insn 67
changing reg in insn 23
changing reg in insn 58
changing reg in insn 73
changing reg in insn 32
changing reg in insn 66
changing reg in insn 9
changing reg in insn 66
changing reg in insn 63
changing reg in insn 67
changing reg in insn 10
changing reg in insn 67
changing reg in insn 76
changing reg in insn 11
changing reg in insn 76
changing reg in insn 83
changing reg in insn 2
changing reg in insn 24
changing reg in insn 16
changing reg in insn 9
changing reg in insn 3
changing reg in insn 16
changing reg in insn 5
changing reg in insn 16
changing reg in insn 17
changing reg in insn 38
changing reg in insn 43
changing reg in insn 43
changing reg in insn 44
changing reg in insn 44
changing reg in insn 45
changing reg in insn 51
changing reg in insn 52
changing reg in insn 109
changing reg in insn 59
changing reg in insn 63
changing reg in insn 64
changing reg in insn 73
changing reg in insn 74
changing reg in insn 101
changing reg in insn 2
changing reg in insn 102
changing reg in insn 3
changing reg in insn 58
changing reg in insn 109
changing reg in insn 17
changing reg in insn 22
changing reg in insn 23
changing reg in insn 38
changing reg in insn 43
changing reg in insn 45
changing reg in insn 52
changing reg in insn 59
changing reg in insn 64
changing reg in insn 66
changing reg in insn 67
changing reg in insn 70
changing reg in insn 71
changing reg in insn 74
deleting insn with uid = 101.
deleting insn with uid = 102.
deleting insn with uid = 3.
deleting insn with uid = 5.
deleting insn with uid = 109.
deleting insn with uid = 9.
deleting insn with uid = 76.
deleting insn with uid = 83.


try_optimize_cfg iteration 1

Forwarding edge 2->3 to 8 failed.
Forwarding edge 5->6 to 8 failed.
Forwarding edge 11->12 to 13 failed.
Deleting fallthru block 12.
deleting block 12


try_optimize_cfg iteration 2

Forwarding edge 2->3 to 8 failed.
Forwarding edge 5->6 to 8 failed.


try_optimize_cfg iteration 1

Forwarding edge 2->3 to 8 failed.
Forwarding edge 5->6 to 8 failed.
starting the processing of deferred insns
ending the processing of deferred insns
starting the processing of deferred insns
ending the processing of deferred insns
df_analyze called
df_worklist_dataflow_doublequeue: n_basic_blocks 13 n_edges 18 count 15 (  1.2)
df_worklist_dataflow_doublequeue: n_basic_blocks 13 n_edges 18 count 15 (  1.2)


__udivsi3

Dataflow summary:
;;  invalidated by call 	 0 [s0] 1 [s1] 2 [s2] 3 [s3] 4 [s4] 5 [s5] 6 [s6] 7 [s7] 8 [s8] 9 [s9] 10 [s10] 11 [s11] 12 [s12] 13 [s13] 15 [s15] 17 [s17] 18 [s18] 19 [s19] 20 [s20] 21 [s21] 22 [s22] 23 [s23] 24 [s24] 25 [s25] 26 [s26] 27 [s27] 28 [s28] 29 [s29] 30 [s30] 31 [s31] 96 [s96] 97 [s97] 98 [s98] 99 [s99] 100 [s100] 101 [s101] 102 [flat_scratch_lo] 103 [flat_scratch_hi] 104 [xnack_mask_lo] 105 [xnack_mask_hi] 106 [vcc_lo] 107 [vcc_hi] 108 [vccz] 109 [tba_lo] 110 [tba_hi] 111 [tma_lo] 112 [tma_hi] 113 [ttmp0] 114 [ttmp1] 115 [ttmp2] 116 [ttmp3] 117 [ttmp4] 118 [ttmp5] 119 [ttmp6] 120 [ttmp7] 121 [ttmp8] 122 [ttmp9] 123 [ttmp10] 124 [ttmp11] 125 [m0] 126 [exec_lo] 127 [exec_hi] 128 [execz] 129 [scc] 130 [res130] 131 [res131] 132 [res132] 133 [res133] 134 [res134] 135 [res135] 136 [res136] 137 [res137] 138 [res138] 139 [res139] 140 [res140] 141 [res141] 142 [res142] 143 [res143] 144 [res144] 145 [res145] 146 [res146] 147 [res147] 148 [res148] 149 [res149] 150 [res150] 151 [res151] 152 [res152] 153 [res153] 154 [res154] 155 [res155] 156 [res156] 157 [res157] 158 [res158] 159 [res159] 160 [v0] 161 [v1] 162 [v2] 163 [v3] 164 [v4] 165 [v5] 166 [v6] 167 [v7] 168 [v8] 169 [v9] 170 [v10] 171 [v11] 172 [v12] 173 [v13] 174 [v14] 175 [v15] 224 [v64] 225 [v65] 226 [v66] 227 [v67] 228 [v68] 229 [v69] 230 [v70] 231 [v71] 232 [v72] 233 [v73] 234 [v74] 235 [v75] 236 [v76] 237 [v77] 238 [v78] 239 [v79] 240 [v80] 241 [v81] 242 [v82] 243 [v83] 244 [v84] 245 [v85] 246 [v86] 247 [v87] 248 [v88] 249 [v89] 250 [v90] 251 [v91] 252 [v92] 253 [v93] 254 [v94] 255 [v95] 256 [v96] 257 [v97] 258 [v98] 259 [v99] 260 [v100] 261 [v101] 262 [v102] 263 [v103] 264 [v104] 265 [v105] 266 [v106] 267 [v107] 268 [v108] 269 [v109] 270 [v110] 271 [v111] 272 [v112] 273 [v113] 274 [v114] 275 [v115] 276 [v116] 277 [v117] 278 [v118] 279 [v119] 280 [v120] 281 [v121] 282 [v122] 283 [v123] 284 [v124] 285 [v125] 286 [v126] 287 [v127] 288 [v128] 289 [v129] 290 [v130] 291 [v131] 292 [v132] 293 [v133] 294 [v134] 295 [v135] 296 [v136] 297 [v137] 298 [v138] 299 [v139] 300 [v140] 301 [v141] 302 [v142] 303 [v143] 304 [v144] 305 [v145] 306 [v146] 307 [v147] 308 [v148] 309 [v149] 310 [v150] 311 [v151] 312 [v152] 313 [v153] 314 [v154] 315 [v155] 316 [v156] 317 [v157] 318 [v158] 319 [v159] 320 [v160] 321 [v161] 322 [v162] 323 [v163] 324 [v164] 325 [v165] 326 [v166] 327 [v167] 328 [v168] 329 [v169] 330 [v170] 331 [v171] 332 [v172] 333 [v173] 334 [v174] 335 [v175] 336 [v176] 337 [v177] 338 [v178] 339 [v179] 340 [v180] 341 [v181] 342 [v182] 343 [v183] 344 [v184] 345 [v185] 346 [v186] 347 [v187] 348 [v188] 349 [v189] 350 [v190] 351 [v191] 352 [v192] 353 [v193] 354 [v194] 355 [v195] 356 [v196] 357 [v197] 358 [v198] 359 [v199] 360 [v200] 361 [v201] 362 [v202] 363 [v203] 364 [v204] 365 [v205] 366 [v206] 367 [v207] 368 [v208] 369 [v209] 370 [v210] 371 [v211] 372 [v212] 373 [v213] 374 [v214] 375 [v215] 376 [v216] 377 [v217] 378 [v218] 379 [v219] 380 [v220] 381 [v221] 382 [v222] 383 [v223] 384 [v224] 385 [v225] 386 [v226] 387 [v227] 388 [v228] 389 [v229] 390 [v230] 391 [v231] 392 [v232] 393 [v233] 394 [v234] 395 [v235] 396 [v236] 397 [v237] 398 [v238] 399 [v239] 400 [v240] 401 [v241] 402 [v242] 403 [v243] 404 [v244] 405 [v245] 406 [v246] 407 [v247] 408 [v248] 409 [v249] 410 [v250] 411 [v251] 412 [v252] 413 [v253] 414 [v254] 415 [v255] 417 [?ap1] 419 [?fp1]
;;  hardware regs used 	 16 [s16]
;;  regular block artificial uses 	 16 [s16]
;;  eh block artificial uses 	 16 [s16] 416 [?ap0]
;;  entry block defs 	 16 [s16] 18 [s18] 24 [s24] 25 [s25] 26 [s26] 27 [s27] 28 [s28] 29 [s29]
;;  exit block uses 	 16 [s16] 24 [s24]
;;  regs ever live 	 18 [s18] 19 [s19] 24 [s24] 25 [s25] 26 [s26] 129 [scc]
;;  ref usage 	r16={1d,12u} r18={4d,3u} r19={3d,6u} r24={5d,5u} r25={3d,7u} r26={3d,4u} r27={1d} r28={1d} r29={1d} r129={22d,8u} 
;;    total ref usage 89{44d,45u,0e} in 31{31 regular + 0 call} insns.
(note 1 0 12 NOTE_INSN_DELETED)
(note 12 1 2 2 [bb 2] NOTE_INSN_BASIC_BLOCK)
(insn 2 12 4 2 (set (reg/v:SI 26 s26 [orig:438 a ] [438])
        (reg:SI 24 s24 [464])) "/scratch/astubbs/amd/upstream/src/gcc-gcn-master/libgcc/config/gcn/lib2-divmod.c":107:1 4 {*movsi_insn}
     (nil))
(note 4 2 16 2 NOTE_INSN_FUNCTION_BEG)
(insn 16 4 6 2 (set (reg:BI 129 scc [440])
        (gtu:BI (reg/v:SI 26 s26 [orig:438 a ] [438])
            (reg/v:SI 25 s25 [orig:439 b ] [439]))) "/scratch/astubbs/amd/upstream/src/gcc-gcn-master/libgcc/config/gcn/lib2-divmod.c":33:9 22 {cstoresi4}
     (nil))
(insn 6 16 17 2 (set (reg/v:SI 19 s19 [orig:429 bit ] [429])
        (const_int 1 [0x1])) "/scratch/astubbs/amd/upstream/src/gcc-gcn-master/libgcc/config/gcn/lib2-divmod.c":30:11 4 {*movsi_insn}
     (expr_list:REG_EQUAL (const_int 1 [0x1])
        (nil)))
(jump_insn 17 6 103 2 (parallel [
            (set (pc)
                (if_then_else (ne:BI (reg:BI 129 scc [440])
                        (const_int 0 [0]))
                    (label_ref:DI 46)
                    (pc)))
            (clobber (reg:BI 129 scc [467]))
        ]) "/scratch/astubbs/amd/upstream/src/gcc-gcn-master/libgcc/config/gcn/lib2-divmod.c":33:9 14 {cjump}
     (int_list:REG_BR_PROB 1014686028 (nil))
 -> 46)
(note 103 17 104 3 [bb 3] NOTE_INSN_BASIC_BLOCK)
(jump_insn 104 103 105 3 (set (pc)
        (label_ref 60)) 12 {jump}
     (nil)
 -> 60)
(barrier 105 104 48)
(code_label 48 105 21 4 47 (nil) [1 uses])
(note 21 48 22 4 [bb 4] NOTE_INSN_BASIC_BLOCK)
(insn 22 21 23 4 (parallel [
            (set (reg/v:SI 25 s25 [orig:428 den ] [428])
                (ashift:SI (reg/v:SI 25 s25 [orig:428 den ] [428])
                    (const_int 1 [0x1])))
            (clobber (reg:BI 129 scc [468]))
        ]) "/scratch/astubbs/amd/upstream/src/gcc-gcn-master/libgcc/config/gcn/lib2-divmod.c":35:11 56 {ashlsi3}
     (nil))
(insn 23 22 24 4 (parallel [
            (set (reg/v:SI 19 s19 [orig:429 bit ] [429])
                (ashift:SI (reg/v:SI 19 s19 [orig:429 bit ] [429])
                    (const_int 1 [0x1])))
            (clobber (reg:BI 129 scc [469]))
        ]) "/scratch/astubbs/amd/upstream/src/gcc-gcn-master/libgcc/config/gcn/lib2-divmod.c":36:11 56 {ashlsi3}
     (nil))
(insn 24 23 111 4 (set (reg:BI 129 scc [442])
        (gtu:BI (reg/v:SI 26 s26 [orig:438 a ] [438])
            (reg/v:SI 25 s25 [orig:428 den ] [428]))) "/scratch/astubbs/amd/upstream/src/gcc-gcn-master/libgcc/config/gcn/lib2-divmod.c":33:14 22 {cstoresi4}
     (nil))
(insn 111 24 25 4 (set (reg:BI 24 s24 [442])
        (reg:BI 129 scc [442])) "/scratch/astubbs/amd/upstream/src/gcc-gcn-master/libgcc/config/gcn/lib2-divmod.c":33:14 3 {*movbi}
     (nil))
(note 25 111 28 4 NOTE_INSN_DELETED)
(note 28 25 29 4 NOTE_INSN_DELETED)
(note 29 28 30 4 NOTE_INSN_DELETED)
(note 30 29 32 4 NOTE_INSN_DELETED)
(insn 32 30 112 4 (set (reg:BI 129 scc [449])
        (ne:BI (reg/v:SI 19 s19 [orig:429 bit ] [429])
            (const_int 0 [0]))) "/scratch/astubbs/amd/upstream/src/gcc-gcn-master/libgcc/config/gcn/lib2-divmod.c":33:20 22 {cstoresi4}
     (nil))
(insn 112 32 33 4 (set (reg:BI 18 s18 [449])
        (reg:BI 129 scc [449])) "/scratch/astubbs/amd/upstream/src/gcc-gcn-master/libgcc/config/gcn/lib2-divmod.c":33:20 3 {*movbi}
     (nil))
(note 33 112 36 4 NOTE_INSN_DELETED)
(note 36 33 37 4 NOTE_INSN_DELETED)
(note 37 36 38 4 NOTE_INSN_DELETED)
(insn 38 37 40 4 (parallel [
            (set (reg:SI 18 s18 [454])
                (and:SI (reg:SI 18 s18 [449])
                    (const_int 1 [0x1])))
            (clobber (reg:BI 129 scc [470]))
        ]) "/scratch/astubbs/amd/upstream/src/gcc-gcn-master/libgcc/config/gcn/lib2-divmod.c":33:20 49 {andsi3}
     (nil))
(note 40 38 42 4 NOTE_INSN_DELETED)
(note 42 40 43 4 NOTE_INSN_DELETED)
(insn 43 42 44 4 (parallel [
            (set (reg:SI 18 s18 [457])
                (and:SI (reg:SI 18 s18 [454])
                    (reg:SI 24 s24 [442])))
            (clobber (reg:BI 129 scc [471]))
        ]) "/scratch/astubbs/amd/upstream/src/gcc-gcn-master/libgcc/config/gcn/lib2-divmod.c":33:9 49 {andsi3}
     (nil))
(insn 44 43 45 4 (set (reg:BI 129 scc [458])
        (eq:BI (reg:SI 18 s18 [457])
            (const_int 0 [0]))) "/scratch/astubbs/amd/upstream/src/gcc-gcn-master/libgcc/config/gcn/lib2-divmod.c":33:9 22 {cstoresi4}
     (nil))
(jump_insn 45 44 46 4 (parallel [
            (set (pc)
                (if_then_else (ne:BI (reg:BI 129 scc [458])
                        (const_int 0 [0]))
                    (label_ref 56)
                    (pc)))
            (clobber (reg:BI 129 scc [472]))
        ]) "/scratch/astubbs/amd/upstream/src/gcc-gcn-master/libgcc/config/gcn/lib2-divmod.c":33:9 14 {cjump}
     (int_list:REG_BR_PROB 59055804 (nil))
 -> 56)
(code_label 46 45 47 5 44 (nil) [1 uses])
(note 47 46 51 5 [bb 5] NOTE_INSN_BASIC_BLOCK)
(insn 51 47 52 5 (set (reg:BI 129 scc [459])
        (ge:BI (reg/v:SI 25 s25 [orig:428 den ] [428])
            (const_int 0 [0]))) "/scratch/astubbs/amd/upstream/src/gcc-gcn-master/libgcc/config/gcn/lib2-divmod.c":33:27 22 {cstoresi4}
     (nil))
(jump_insn 52 51 106 5 (parallel [
            (set (pc)
                (if_then_else (ne:BI (reg:BI 129 scc [459])
                        (const_int 0 [0]))
                    (label_ref 48)
                    (pc)))
            (clobber (reg:BI 129 scc [473]))
        ]) "/scratch/astubbs/amd/upstream/src/gcc-gcn-master/libgcc/config/gcn/lib2-divmod.c":33:27 14 {cjump}
     (int_list:REG_BR_PROB 1014686028 (nil))
 -> 48)
(note 106 52 107 6 [bb 6] NOTE_INSN_BASIC_BLOCK)
(jump_insn 107 106 108 6 (set (pc)
        (label_ref 60)) 12 {jump}
     (nil)
 -> 60)
(barrier 108 107 56)
(code_label 56 108 57 7 46 (nil) [1 uses])
(note 57 56 58 7 [bb 7] NOTE_INSN_BASIC_BLOCK)
(insn 58 57 11 7 (set (reg:BI 129 scc [460])
        (eq:BI (reg/v:SI 19 s19 [orig:429 bit ] [429])
            (const_int 0 [0]))) "/scratch/astubbs/amd/upstream/src/gcc-gcn-master/libgcc/config/gcn/lib2-divmod.c":38:9 22 {cstoresi4}
     (nil))
(insn 11 58 59 7 (set (reg:SI 24 s24 [orig:436 prephitmp_35 ] [436])
        (const_int 0 [0])) "/scratch/astubbs/amd/upstream/src/gcc-gcn-master/libgcc/config/gcn/lib2-divmod.c":38:9 4 {*movsi_insn}
     (expr_list:REG_EQUAL (const_int 0 [0])
        (nil)))
(jump_insn 59 11 60 7 (parallel [
            (set (pc)
                (if_then_else (ne:BI (reg:BI 129 scc [460])
                        (const_int 0 [0]))
                    (label_ref:DI 77)
                    (pc)))
            (clobber (reg:BI 129 scc [474]))
        ]) "/scratch/astubbs/amd/upstream/src/gcc-gcn-master/libgcc/config/gcn/lib2-divmod.c":38:9 14 {cjump}
     (int_list:REG_BR_PROB 258120292 (nil))
 -> 77)
(code_label 60 59 61 8 45 (nil) [2 uses])
(note 61 60 10 8 [bb 8] NOTE_INSN_BASIC_BLOCK)
(insn 10 61 72 8 (set (reg/v:SI 24 s24 [orig:435 res ] [435])
        (const_int 0 [0])) "/scratch/astubbs/amd/upstream/src/gcc-gcn-master/libgcc/config/gcn/lib2-divmod.c":108:10 4 {*movsi_insn}
     (expr_list:REG_EQUAL (const_int 0 [0])
        (nil)))
(code_label 72 10 62 9 50 (nil) [1 uses])
(note 62 72 63 9 [bb 9] NOTE_INSN_BASIC_BLOCK)
(insn 63 62 64 9 (set (reg:BI 129 scc [461])
        (ltu:BI (reg/v:SI 26 s26 [orig:434 num ] [434])
            (reg/v:SI 25 s25 [orig:428 den ] [428]))) "/scratch/astubbs/amd/upstream/src/gcc-gcn-master/libgcc/config/gcn/lib2-divmod.c":40:10 22 {cstoresi4}
     (nil))
(jump_insn 64 63 65 9 (parallel [
            (set (pc)
                (if_then_else (ne:BI (reg:BI 129 scc [461])
                        (const_int 0 [0]))
                    (label_ref 68)
                    (pc)))
            (clobber (reg:BI 129 scc [475]))
        ]) "/scratch/astubbs/amd/upstream/src/gcc-gcn-master/libgcc/config/gcn/lib2-divmod.c":40:10 14 {cjump}
     (int_list:REG_BR_PROB 536870916 (nil))
 -> 68)
(note 65 64 66 10 [bb 10] NOTE_INSN_BASIC_BLOCK)
(insn 66 65 67 10 (parallel [
            (set (reg/v:SI 26 s26 [orig:434 num ] [434])
                (minus:SI (reg/v:SI 26 s26 [orig:434 num ] [434])
                    (reg/v:SI 25 s25 [orig:428 den ] [428])))
            (clobber (reg:BI 129 scc [476]))
            (clobber (scratch:DI))
        ]) "/scratch/astubbs/amd/upstream/src/gcc-gcn-master/libgcc/config/gcn/lib2-divmod.c":42:8 34 {subsi3}
     (nil))
(insn 67 66 68 10 (parallel [
            (set (reg/v:SI 24 s24 [orig:435 res ] [435])
                (ior:SI (reg/v:SI 24 s24 [orig:435 res ] [435])
                    (reg/v:SI 19 s19 [orig:429 bit ] [429])))
            (clobber (reg:BI 129 scc [478]))
        ]) "/scratch/astubbs/amd/upstream/src/gcc-gcn-master/libgcc/config/gcn/lib2-divmod.c":43:8 50 {iorsi3}
     (nil))
(code_label 68 67 69 11 49 (nil) [1 uses])
(note 69 68 70 11 [bb 11] NOTE_INSN_BASIC_BLOCK)
(insn 70 69 71 11 (parallel [
            (set (reg/v:SI 19 s19 [orig:429 bit ] [429])
                (lshiftrt:SI (reg/v:SI 19 s19 [orig:429 bit ] [429])
                    (const_int 1 [0x1])))
            (clobber (reg:BI 129 scc [479]))
        ]) "/scratch/astubbs/amd/upstream/src/gcc-gcn-master/libgcc/config/gcn/lib2-divmod.c":45:11 57 {lshrsi3}
     (nil))
(insn 71 70 73 11 (parallel [
            (set (reg/v:SI 25 s25 [orig:428 den ] [428])
                (lshiftrt:SI (reg/v:SI 25 s25 [orig:428 den ] [428])
                    (const_int 1 [0x1])))
            (clobber (reg:BI 129 scc [480]))
        ]) "/scratch/astubbs/amd/upstream/src/gcc-gcn-master/libgcc/config/gcn/lib2-divmod.c":46:11 57 {lshrsi3}
     (nil))
(insn 73 71 74 11 (set (reg:BI 129 scc [462])
        (ne:BI (reg/v:SI 19 s19 [orig:429 bit ] [429])
            (const_int 0 [0]))) "/scratch/astubbs/amd/upstream/src/gcc-gcn-master/libgcc/config/gcn/lib2-divmod.c":38:9 22 {cstoresi4}
     (nil))
(jump_insn 74 73 77 11 (parallel [
            (set (pc)
                (if_then_else (ne:BI (reg:BI 129 scc [462])
                        (const_int 0 [0]))
                    (label_ref:DI 72)
                    (pc)))
            (clobber (reg:BI 129 scc [481]))
        ]) "/scratch/astubbs/amd/upstream/src/gcc-gcn-master/libgcc/config/gcn/lib2-divmod.c":38:9 14 {cjump}
     (int_list:REG_BR_PROB 955630228 (nil))
 -> 72)
(code_label 77 74 78 13 48 (nil) [1 uses])
(note 78 77 84 13 [bb 13] NOTE_INSN_BASIC_BLOCK)
(insn 84 78 110 13 (use (reg/i:SI 24 s24)) "/scratch/astubbs/amd/upstream/src/gcc-gcn-master/libgcc/config/gcn/lib2-divmod.c":109:1 -1
     (nil))
(note 110 84 0 NOTE_INSN_DELETED)
;; Function __udivsi3 (__udivsi3, funcdef_no=3, decl_uid=1439, cgraph_uid=4, symbol_order=3)



try_optimize_cfg iteration 1

verify found no changes in insn with uid = 17.
Edge 2->5 redirected to 4
Conditionals threaded.
Forwarding edge 2->3 to 8 failed.
Forwarding edge 2->3 to 8 failed.
changing bb of uid 113
  unscanned insn
scanning new insn with uid = 114.
Conditionals threaded.
Forwarding edge 4->13 to 8 failed.
Forwarding edge 4->13 to 8 failed.
deleting insn with uid = 52.
deleting insn with uid = 51.
deleting block 5
deleting insn with uid = 107.
deleting block 6


try_optimize_cfg iteration 2

Forwarding edge 2->3 to 8 failed.
Forwarding edge 4->13 to 8 failed.


try_optimize_cfg iteration 1

Forwarding edge 2->3 to 8 failed.
Forwarding edge 4->13 to 8 failed.


__udivsi3

Dataflow summary:
;;  invalidated by call 	 0 [s0] 1 [s1] 2 [s2] 3 [s3] 4 [s4] 5 [s5] 6 [s6] 7 [s7] 8 [s8] 9 [s9] 10 [s10] 11 [s11] 12 [s12] 13 [s13] 15 [s15] 17 [s17] 18 [s18] 19 [s19] 20 [s20] 21 [s21] 22 [s22] 23 [s23] 24 [s24] 25 [s25] 26 [s26] 27 [s27] 28 [s28] 29 [s29] 30 [s30] 31 [s31] 96 [s96] 97 [s97] 98 [s98] 99 [s99] 100 [s100] 101 [s101] 102 [flat_scratch_lo] 103 [flat_scratch_hi] 104 [xnack_mask_lo] 105 [xnack_mask_hi] 106 [vcc_lo] 107 [vcc_hi] 108 [vccz] 109 [tba_lo] 110 [tba_hi] 111 [tma_lo] 112 [tma_hi] 113 [ttmp0] 114 [ttmp1] 115 [ttmp2] 116 [ttmp3] 117 [ttmp4] 118 [ttmp5] 119 [ttmp6] 120 [ttmp7] 121 [ttmp8] 122 [ttmp9] 123 [ttmp10] 124 [ttmp11] 125 [m0] 126 [exec_lo] 127 [exec_hi] 128 [execz] 129 [scc] 130 [res130] 131 [res131] 132 [res132] 133 [res133] 134 [res134] 135 [res135] 136 [res136] 137 [res137] 138 [res138] 139 [res139] 140 [res140] 141 [res141] 142 [res142] 143 [res143] 144 [res144] 145 [res145] 146 [res146] 147 [res147] 148 [res148] 149 [res149] 150 [res150] 151 [res151] 152 [res152] 153 [res153] 154 [res154] 155 [res155] 156 [res156] 157 [res157] 158 [res158] 159 [res159] 160 [v0] 161 [v1] 162 [v2] 163 [v3] 164 [v4] 165 [v5] 166 [v6] 167 [v7] 168 [v8] 169 [v9] 170 [v10] 171 [v11] 172 [v12] 173 [v13] 174 [v14] 175 [v15] 224 [v64] 225 [v65] 226 [v66] 227 [v67] 228 [v68] 229 [v69] 230 [v70] 231 [v71] 232 [v72] 233 [v73] 234 [v74] 235 [v75] 236 [v76] 237 [v77] 238 [v78] 239 [v79] 240 [v80] 241 [v81] 242 [v82] 243 [v83] 244 [v84] 245 [v85] 246 [v86] 247 [v87] 248 [v88] 249 [v89] 250 [v90] 251 [v91] 252 [v92] 253 [v93] 254 [v94] 255 [v95] 256 [v96] 257 [v97] 258 [v98] 259 [v99] 260 [v100] 261 [v101] 262 [v102] 263 [v103] 264 [v104] 265 [v105] 266 [v106] 267 [v107] 268 [v108] 269 [v109] 270 [v110] 271 [v111] 272 [v112] 273 [v113] 274 [v114] 275 [v115] 276 [v116] 277 [v117] 278 [v118] 279 [v119] 280 [v120] 281 [v121] 282 [v122] 283 [v123] 284 [v124] 285 [v125] 286 [v126] 287 [v127] 288 [v128] 289 [v129] 290 [v130] 291 [v131] 292 [v132] 293 [v133] 294 [v134] 295 [v135] 296 [v136] 297 [v137] 298 [v138] 299 [v139] 300 [v140] 301 [v141] 302 [v142] 303 [v143] 304 [v144] 305 [v145] 306 [v146] 307 [v147] 308 [v148] 309 [v149] 310 [v150] 311 [v151] 312 [v152] 313 [v153] 314 [v154] 315 [v155] 316 [v156] 317 [v157] 318 [v158] 319 [v159] 320 [v160] 321 [v161] 322 [v162] 323 [v163] 324 [v164] 325 [v165] 326 [v166] 327 [v167] 328 [v168] 329 [v169] 330 [v170] 331 [v171] 332 [v172] 333 [v173] 334 [v174] 335 [v175] 336 [v176] 337 [v177] 338 [v178] 339 [v179] 340 [v180] 341 [v181] 342 [v182] 343 [v183] 344 [v184] 345 [v185] 346 [v186] 347 [v187] 348 [v188] 349 [v189] 350 [v190] 351 [v191] 352 [v192] 353 [v193] 354 [v194] 355 [v195] 356 [v196] 357 [v197] 358 [v198] 359 [v199] 360 [v200] 361 [v201] 362 [v202] 363 [v203] 364 [v204] 365 [v205] 366 [v206] 367 [v207] 368 [v208] 369 [v209] 370 [v210] 371 [v211] 372 [v212] 373 [v213] 374 [v214] 375 [v215] 376 [v216] 377 [v217] 378 [v218] 379 [v219] 380 [v220] 381 [v221] 382 [v222] 383 [v223] 384 [v224] 385 [v225] 386 [v226] 387 [v227] 388 [v228] 389 [v229] 390 [v230] 391 [v231] 392 [v232] 393 [v233] 394 [v234] 395 [v235] 396 [v236] 397 [v237] 398 [v238] 399 [v239] 400 [v240] 401 [v241] 402 [v242] 403 [v243] 404 [v244] 405 [v245] 406 [v246] 407 [v247] 408 [v248] 409 [v249] 410 [v250] 411 [v251] 412 [v252] 413 [v253] 414 [v254] 415 [v255] 417 [?ap1] 419 [?fp1]
;;  hardware regs used 	 16 [s16]
;;  regular block artificial uses 	 16 [s16]
;;  eh block artificial uses 	 16 [s16] 416 [?ap0]
;;  entry block defs 	 16 [s16] 18 [s18] 24 [s24] 25 [s25] 26 [s26] 27 [s27] 28 [s28] 29 [s29]
;;  exit block uses 	 16 [s16] 24 [s24]
;;  regs ever live 	 18 [s18] 19 [s19] 24 [s24] 25 [s25] 26 [s26] 129 [scc]
;;  ref usage 	r16={1d,11u} r18={4d,3u} r19={3d,6u} r24={5d,5u} r25={3d,6u} r26={3d,4u} r27={1d} r28={1d} r29={1d} r129={20d,7u} 
;;    total ref usage 84{42d,42u,0e} in 29{29 regular + 0 call} insns.
(note 1 0 12 NOTE_INSN_DELETED)
(note 12 1 2 2 [bb 2] NOTE_INSN_BASIC_BLOCK)
(insn 2 12 4 2 (set (reg/v:SI 26 s26 [orig:438 a ] [438])
        (reg:SI 24 s24 [464])) "/scratch/astubbs/amd/upstream/src/gcc-gcn-master/libgcc/config/gcn/lib2-divmod.c":107:1 4 {*movsi_insn}
     (nil))
(note 4 2 16 2 NOTE_INSN_FUNCTION_BEG)
(insn 16 4 6 2 (set (reg:BI 129 scc [440])
        (gtu:BI (reg/v:SI 26 s26 [orig:438 a ] [438])
            (reg/v:SI 25 s25 [orig:439 b ] [439]))) "/scratch/astubbs/amd/upstream/src/gcc-gcn-master/libgcc/config/gcn/lib2-divmod.c":33:9 22 {cstoresi4}
     (nil))
(insn 6 16 17 2 (set (reg/v:SI 19 s19 [orig:429 bit ] [429])
        (const_int 1 [0x1])) "/scratch/astubbs/amd/upstream/src/gcc-gcn-master/libgcc/config/gcn/lib2-divmod.c":30:11 4 {*movsi_insn}
     (expr_list:REG_EQUAL (const_int 1 [0x1])
        (nil)))
(jump_insn 17 6 103 2 (parallel [
            (set (pc)
                (if_then_else (ne:BI (reg:BI 129 scc [440])
                        (const_int 0 [0]))
                    (label_ref:DI 48)
                    (pc)))
            (clobber (reg:BI 129 scc [467]))
        ]) "/scratch/astubbs/amd/upstream/src/gcc-gcn-master/libgcc/config/gcn/lib2-divmod.c":33:9 14 {cjump}
     (int_list:REG_BR_PROB 1014686028 (nil))
 -> 48)
(note 103 17 104 3 [bb 3] NOTE_INSN_BASIC_BLOCK)
(jump_insn 104 103 105 3 (set (pc)
        (label_ref 60)) 12 {jump}
     (nil)
 -> 60)
(barrier 105 104 48)
(code_label 48 105 21 4 47 (nil) [1 uses])
(note 21 48 22 4 [bb 4] NOTE_INSN_BASIC_BLOCK)
(insn 22 21 23 4 (parallel [
            (set (reg/v:SI 25 s25 [orig:428 den ] [428])
                (ashift:SI (reg/v:SI 25 s25 [orig:428 den ] [428])
                    (const_int 1 [0x1])))
            (clobber (reg:BI 129 scc [468]))
        ]) "/scratch/astubbs/amd/upstream/src/gcc-gcn-master/libgcc/config/gcn/lib2-divmod.c":35:11 56 {ashlsi3}
     (nil))
(insn 23 22 24 4 (parallel [
            (set (reg/v:SI 19 s19 [orig:429 bit ] [429])
                (ashift:SI (reg/v:SI 19 s19 [orig:429 bit ] [429])
                    (const_int 1 [0x1])))
            (clobber (reg:BI 129 scc [469]))
        ]) "/scratch/astubbs/amd/upstream/src/gcc-gcn-master/libgcc/config/gcn/lib2-divmod.c":36:11 56 {ashlsi3}
     (nil))
(insn 24 23 111 4 (set (reg:BI 129 scc [442])
        (gtu:BI (reg/v:SI 26 s26 [orig:438 a ] [438])
            (reg/v:SI 25 s25 [orig:428 den ] [428]))) "/scratch/astubbs/amd/upstream/src/gcc-gcn-master/libgcc/config/gcn/lib2-divmod.c":33:14 22 {cstoresi4}
     (nil))
(insn 111 24 25 4 (set (reg:BI 24 s24 [442])
        (reg:BI 129 scc [442])) "/scratch/astubbs/amd/upstream/src/gcc-gcn-master/libgcc/config/gcn/lib2-divmod.c":33:14 3 {*movbi}
     (nil))
(note 25 111 28 4 NOTE_INSN_DELETED)
(note 28 25 29 4 NOTE_INSN_DELETED)
(note 29 28 30 4 NOTE_INSN_DELETED)
(note 30 29 32 4 NOTE_INSN_DELETED)
(insn 32 30 112 4 (set (reg:BI 129 scc [449])
        (ne:BI (reg/v:SI 19 s19 [orig:429 bit ] [429])
            (const_int 0 [0]))) "/scratch/astubbs/amd/upstream/src/gcc-gcn-master/libgcc/config/gcn/lib2-divmod.c":33:20 22 {cstoresi4}
     (nil))
(insn 112 32 33 4 (set (reg:BI 18 s18 [449])
        (reg:BI 129 scc [449])) "/scratch/astubbs/amd/upstream/src/gcc-gcn-master/libgcc/config/gcn/lib2-divmod.c":33:20 3 {*movbi}
     (nil))
(note 33 112 36 4 NOTE_INSN_DELETED)
(note 36 33 37 4 NOTE_INSN_DELETED)
(note 37 36 38 4 NOTE_INSN_DELETED)
(insn 38 37 40 4 (parallel [
            (set (reg:SI 18 s18 [454])
                (and:SI (reg:SI 18 s18 [449])
                    (const_int 1 [0x1])))
            (clobber (reg:BI 129 scc [470]))
        ]) "/scratch/astubbs/amd/upstream/src/gcc-gcn-master/libgcc/config/gcn/lib2-divmod.c":33:20 49 {andsi3}
     (nil))
(note 40 38 42 4 NOTE_INSN_DELETED)
(note 42 40 43 4 NOTE_INSN_DELETED)
(insn 43 42 44 4 (parallel [
            (set (reg:SI 18 s18 [457])
                (and:SI (reg:SI 18 s18 [454])
                    (reg:SI 24 s24 [442])))
            (clobber (reg:BI 129 scc [471]))
        ]) "/scratch/astubbs/amd/upstream/src/gcc-gcn-master/libgcc/config/gcn/lib2-divmod.c":33:9 49 {andsi3}
     (nil))
(insn 44 43 45 4 (set (reg:BI 129 scc [458])
        (eq:BI (reg:SI 18 s18 [457])
            (const_int 0 [0]))) "/scratch/astubbs/amd/upstream/src/gcc-gcn-master/libgcc/config/gcn/lib2-divmod.c":33:9 22 {cstoresi4}
     (nil))
(jump_insn 45 44 113 4 (parallel [
            (set (pc)
                (if_then_else (ne:BI (reg:BI 129 scc [458])
                        (const_int 0 [0]))
                    (label_ref 56)
                    (pc)))
            (clobber (reg:BI 129 scc [472]))
        ]) "/scratch/astubbs/amd/upstream/src/gcc-gcn-master/libgcc/config/gcn/lib2-divmod.c":33:9 14 {cjump}
     (int_list:REG_BR_PROB 59055804 (nil))
 -> 56)
(note 113 45 114 13 [bb 13] NOTE_INSN_BASIC_BLOCK)
(jump_insn 114 113 115 13 (set (pc)
        (label_ref 60)) -1
     (nil)
 -> 60)
(barrier 115 114 56)
(code_label 56 115 57 7 46 (nil) [1 uses])
(note 57 56 58 7 [bb 7] NOTE_INSN_BASIC_BLOCK)
(insn 58 57 11 7 (set (reg:BI 129 scc [460])
        (eq:BI (reg/v:SI 19 s19 [orig:429 bit ] [429])
            (const_int 0 [0]))) "/scratch/astubbs/amd/upstream/src/gcc-gcn-master/libgcc/config/gcn/lib2-divmod.c":38:9 22 {cstoresi4}
     (nil))
(insn 11 58 59 7 (set (reg:SI 24 s24 [orig:436 prephitmp_35 ] [436])
        (const_int 0 [0])) "/scratch/astubbs/amd/upstream/src/gcc-gcn-master/libgcc/config/gcn/lib2-divmod.c":38:9 4 {*movsi_insn}
     (expr_list:REG_EQUAL (const_int 0 [0])
        (nil)))
(jump_insn 59 11 60 7 (parallel [
            (set (pc)
                (if_then_else (ne:BI (reg:BI 129 scc [460])
                        (const_int 0 [0]))
                    (label_ref:DI 77)
                    (pc)))
            (clobber (reg:BI 129 scc [474]))
        ]) "/scratch/astubbs/amd/upstream/src/gcc-gcn-master/libgcc/config/gcn/lib2-divmod.c":38:9 14 {cjump}
     (int_list:REG_BR_PROB 258120292 (nil))
 -> 77)
(code_label 60 59 61 8 45 (nil) [2 uses])
(note 61 60 10 8 [bb 8] NOTE_INSN_BASIC_BLOCK)
(insn 10 61 72 8 (set (reg/v:SI 24 s24 [orig:435 res ] [435])
        (const_int 0 [0])) "/scratch/astubbs/amd/upstream/src/gcc-gcn-master/libgcc/config/gcn/lib2-divmod.c":108:10 4 {*movsi_insn}
     (expr_list:REG_EQUAL (const_int 0 [0])
        (nil)))
(code_label 72 10 62 9 50 (nil) [1 uses])
(note 62 72 63 9 [bb 9] NOTE_INSN_BASIC_BLOCK)
(insn 63 62 64 9 (set (reg:BI 129 scc [461])
        (ltu:BI (reg/v:SI 26 s26 [orig:434 num ] [434])
            (reg/v:SI 25 s25 [orig:428 den ] [428]))) "/scratch/astubbs/amd/upstream/src/gcc-gcn-master/libgcc/config/gcn/lib2-divmod.c":40:10 22 {cstoresi4}
     (nil))
(jump_insn 64 63 65 9 (parallel [
            (set (pc)
                (if_then_else (ne:BI (reg:BI 129 scc [461])
                        (const_int 0 [0]))
                    (label_ref 68)
                    (pc)))
            (clobber (reg:BI 129 scc [475]))
        ]) "/scratch/astubbs/amd/upstream/src/gcc-gcn-master/libgcc/config/gcn/lib2-divmod.c":40:10 14 {cjump}
     (int_list:REG_BR_PROB 536870916 (nil))
 -> 68)
(note 65 64 66 10 [bb 10] NOTE_INSN_BASIC_BLOCK)
(insn 66 65 67 10 (parallel [
            (set (reg/v:SI 26 s26 [orig:434 num ] [434])
                (minus:SI (reg/v:SI 26 s26 [orig:434 num ] [434])
                    (reg/v:SI 25 s25 [orig:428 den ] [428])))
            (clobber (reg:BI 129 scc [476]))
            (clobber (scratch:DI))
        ]) "/scratch/astubbs/amd/upstream/src/gcc-gcn-master/libgcc/config/gcn/lib2-divmod.c":42:8 34 {subsi3}
     (nil))
(insn 67 66 68 10 (parallel [
            (set (reg/v:SI 24 s24 [orig:435 res ] [435])
                (ior:SI (reg/v:SI 24 s24 [orig:435 res ] [435])
                    (reg/v:SI 19 s19 [orig:429 bit ] [429])))
            (clobber (reg:BI 129 scc [478]))
        ]) "/scratch/astubbs/amd/upstream/src/gcc-gcn-master/libgcc/config/gcn/lib2-divmod.c":43:8 50 {iorsi3}
     (nil))
(code_label 68 67 69 11 49 (nil) [1 uses])
(note 69 68 70 11 [bb 11] NOTE_INSN_BASIC_BLOCK)
(insn 70 69 71 11 (parallel [
            (set (reg/v:SI 19 s19 [orig:429 bit ] [429])
                (lshiftrt:SI (reg/v:SI 19 s19 [orig:429 bit ] [429])
                    (const_int 1 [0x1])))
            (clobber (reg:BI 129 scc [479]))
        ]) "/scratch/astubbs/amd/upstream/src/gcc-gcn-master/libgcc/config/gcn/lib2-divmod.c":45:11 57 {lshrsi3}
     (nil))
(insn 71 70 73 11 (parallel [
            (set (reg/v:SI 25 s25 [orig:428 den ] [428])
                (lshiftrt:SI (reg/v:SI 25 s25 [orig:428 den ] [428])
                    (const_int 1 [0x1])))
            (clobber (reg:BI 129 scc [480]))
        ]) "/scratch/astubbs/amd/upstream/src/gcc-gcn-master/libgcc/config/gcn/lib2-divmod.c":46:11 57 {lshrsi3}
     (nil))
(insn 73 71 74 11 (set (reg:BI 129 scc [462])
        (ne:BI (reg/v:SI 19 s19 [orig:429 bit ] [429])
            (const_int 0 [0]))) "/scratch/astubbs/amd/upstream/src/gcc-gcn-master/libgcc/config/gcn/lib2-divmod.c":38:9 22 {cstoresi4}
     (nil))
(jump_insn 74 73 77 11 (parallel [
            (set (pc)
                (if_then_else (ne:BI (reg:BI 129 scc [462])
                        (const_int 0 [0]))
                    (label_ref:DI 72)
                    (pc)))
            (clobber (reg:BI 129 scc [481]))
        ]) "/scratch/astubbs/amd/upstream/src/gcc-gcn-master/libgcc/config/gcn/lib2-divmod.c":38:9 14 {cjump}
     (int_list:REG_BR_PROB 955630228 (nil))
 -> 72)
(code_label 77 74 78 12 48 (nil) [1 uses])
(note 78 77 84 12 [bb 12] NOTE_INSN_BASIC_BLOCK)
(insn 84 78 110 12 (use (reg/i:SI 24 s24)) "/scratch/astubbs/amd/upstream/src/gcc-gcn-master/libgcc/config/gcn/lib2-divmod.c":109:1 -1
     (nil))
(note 110 84 0 NOTE_INSN_DELETED)

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