Re: Handling prefetcher tag collisions while allocating registers

[Richard Biener <richard dot guenther at gmail dot com>]

On Tue, Oct 24, 2017 at 1:44 AM, Kugan Vivekanandarajah
<kugan.vivekanandarajah@linaro.org> wrote:
> Hi All,
>
> I am wondering if there is anyway we can prefer certain registers in
> register allocations. That is, I want to have some way of recording
> register allocation decisions (for loads in loop that are accessed in
> steps) and use this to influence register allocation of other loads
> (again that are accessed in steps).
>
> This is for architectures (like falkor AArch64) that use hardware
> perefetchers that use signatures of the loads to lock into and tune
> prefetching parameters. Ideally, If the loads are from the same
> stream, they should have same signature and if they are from different
> stream, they should have different signature. Destination, base
> register and offset are used in the signature. Therefore, selecting
> different register can influence this.
>
> In LLVM, this is implemented as a machine specific pass that runs
> after register allocation. It then inserts mov instruction with
> scratch registers to manage this. We can do a machine reorg pass in
> gcc but detecting strided loads at that stage is not easy.
>
> I am trying to implement this in gcc and wondering what is the
> preferred and acceptable way to implement this. Any thoughts ?

I see nothing but a machine-dependent reorg pass that can do this.

RA and CSE should already end up using the same base registers
for equal streams if possible.  Forcing the same addressing mode
is more difficult I guess but usually this should happen.

As Bin suggests whatever Falkor does seems to be somewhat stupid.

Richard.

> Thanks,
> Kugan