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Re: volatile access optimization (C++ / x86_64)
- From: Matt Godbolt <matt at godbolt dot org>
- To: DJ Delorie <dj at redhat dot com>
- Cc: GCC Development <gcc at gcc dot gnu dot org>
- Date: Mon, 5 Jan 2015 12:31:21 -0600
- Subject: Re: volatile access optimization (C++ / x86_64)
- Authentication-results: sourceware.org; auth=none
- References: <CAFWXXN3quEdSnaoWuPcQn2k-F99Yaw+6=NqgFgcu9ABpv5ZD3Q at mail dot gmail dot com> <xnvbkldsgz dot fsf at greed dot delorie dot com>
On Mon, Jan 5, 2015 at 11:53 AM, DJ Delorie <dj@redhat.com> wrote:
>
> Matt Godbolt <matt@godbolt.org> writes:
>> GCC's code generation uses a "load; add; store" for volatiles, instead
>> of a single "add 1, [metric]".
>
> GCC doesn't know if a target's load/add/store patterns are
> volatile-safe, so it must avoid them. There are a few targets that have
> been audited for volatile-safe-ness such that gcc *can* use the combined
> load/add/store when the backend says it's OK. x86 is not yet one of
> those targets.
Thanks DJ.
One question: do you have an example of a non-volatile-safe machine so
I can get a feel for the problems one might encounter? At best I can
imagine a machine that optimizes "add 0, [mem]" to avoid the
read/write, but I'm not aware of such an ISA.
Much appreciated, Matt