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Re: MSP430 in gcc4.9 ... enable interrupts?
- From: David Brown <david dot brown at hesbynett dot no>
- To: DJ Delorie <dj at redhat dot com>
- Cc: brian at shapes dot demon dot co dot uk, gcc at gcc dot gnu dot org
- Date: Tue, 18 Feb 2014 09:01:43 +0100
- Subject: Re: MSP430 in gcc4.9 ... enable interrupts?
- Authentication-results: sourceware.org; auth=none
- References: <1392372773 dot 17088 dot 27 dot camel at Gannet dot Four> <201402141917 dot s1EJHb0H008351 at greed dot delorie dot com> <5300CAA2 dot 7090208 at hesbynett dot no> <201402172312 dot s1HNCY0I024357 at greed dot delorie dot com>
On 18/02/14 00:12, DJ Delorie wrote:
>> I presume these will be part of the headers for the library
>> distributed for msp430 gcc by TI/Redhat?
>
> I can't speak for TI's or Red Hat's plans. GNU's typical non-custom
> embedded runtime is newlib/libgloss, which usually doesn't have that
> much in the way of chip-specific headers or library functions.
Fair enough. I don't know if Red Hat will be distributing anything
themselves, but I'm confident that TI will distribute chip-specific
headers with pre-built msp430 gcc packages (their aim, after all, is to
get more people to buy msp430 chips - and making the tools as easy and
powerful as possible is part of that). I was just wondering where these
headers would fit in.
>
>> is that for the "critical" attribute that exists in the old msp430
>> port (which disables interrupts for the duration of the function)?
>
> Yes, for things like that. They're documented under "Function
> Attributes" in the "Extensions to the C Language Family" chapter of
> the current GCC manual.
>
Ah yes, I missed it when I first looked - the documentation makes
"critical" look like an option to the "interrupt" attribute, rather than
a stand-alone attribute. It seems to me a rather strange idea to have
both "interrupt" and "critical" on the same function - an "interrupt"
function is inherently "critical" (and "reentrant") in that interrupts
are disabled before it enters, and restored or re-enabled on exit. It
would make a difference on processors like ARMs with several interrupt
levels, but not on an msp430 with its single level.
David