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Testing and branching with different modes
- From: "Paulo Matos" <pmatos at broadcom dot com>
- To: "gcc at gcc dot gnu dot org" <gcc at gcc dot gnu dot org>
- Date: Thu, 6 Jun 2013 16:18:12 +0000
- Subject: Testing and branching with different modes
Hello,
My port seems to be slightly awkward in testing and branching compared to the existing one in mainline.
All the comparisons in my port set a QImode (8bits) register (predicate register), however branches branch on a single bit value of the predicate register.
So while I have:
tsteqb p0, r0, r1
which sets p0 to 0xff is r0 == r1, then the branch looks like
bl p0.<bit>, <label>,
where
bl p0.0, L1
branches to L1 is bit 0 of p0 is set.
So I have cmp_qimode, etc but then only cbranchbi4.
My cbranchbi4 should look like this:
(define_insn "cbranchbi4"
[(set (pc)
(if_then_else
(match_operator 0 " easy_comparison"
[(subreg:BI (match_operand:QI 1 "register" "c") 0)
(match_operand:BI 2 "const0" "")])
(label_ref (match_operand 3 "" ""))
(pc)))]
""...
or
(define_insn "cbranchbi4"
[(set (pc)
(if_then_else
(match_operator 0 " easy_comparison"
[(and:BI (match_operand:QI 1 " register" "c")
(const_int 1))
(match_operand:BI 2 "const0" "")])
(label_ref (match_operand 3 "" ""))
(pc)))]
""...
but both of these alternatives don't seem to be supported as it causes an ICE in patch_jump_insn.
What's the best way to deal with this situation? Is there any port out there with similar issues?
Cheers,
Paulo Matos