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Reload and addsi
- From: Hendrik Greving <hendrik dot greving dot intel at gmail dot com>
- To: gcc at gcc dot gnu dot org
- Date: Wed, 5 Jun 2013 09:14:32 -0700
- Subject: Reload and addsi
I am looking at a case (old GCC 3.2.3 is used), which I like to
outline as follow:
00.rtl:
====
(insn 2219 2218 2220 (nil) (set (reg:SI 1296)
(plus:SI (subreg:SI (reg/v:HI 1277) 0)
(const_int 1 [0x1]))) -1 (nil)
(nil))
(insn 2220 2219 2221 (nil) (set (reg/v:HI 1277)
(subreg:HI (reg:SI 1296) 0)) -1 (nil)
(nil))
20.regmove:
=========
(insn 2219 2218 2220 60 0x2aaaad83aa80 (set (reg:SI 1296)
(plus:SI (subreg:SI (reg/v:HI 879) 0)
(const_int 1 [0x1]))) 9 {addsi3} (nil)
(expr_list:REG_DEAD (reg/v:HI 879)
(nil)))
(insn 2220 2219 2221 60 0x2aaaad83aa80 (set (reg/v:HI 1277)
(subreg:HI (reg:SI 1296) 0)) 79 {*movhi_i} (insn_list 2219 (nil))
(nil))
22.lreg:
=====
(insn 5044 2227 5045 60 (nil) (set (reg:SI 45 r45)
(plus:SI (reg/f:SI 323 sp)
(const_int 144 [0x90]))) 9 {addsi3} (nil)
(nil))
(insn 5045 5044 2219 60 (nil) (set (reg:SI 45 r45)
(mem:SI (reg:SI 45 r45) [9442 sec 0 space 0, cmsmode 0
x86_nmbr S2 A16])) 74 {*movsi} (nil)
(nil))
(insn 2219 5045 2221 60 0x2aaaad83aa80 (set (reg:SI 46 r46 [1296])
(plus:SI (reg:SI 45 r45)
(const_int 1 [0x1]))) 9 {addsi3} (nil)
(nil))
23.greg:
======
(insn 2219 2227 2221 60 0x2aaaad83aa80 (set (reg:SI 1296)
(plus:SI (subreg:SI (reg/v:HI 879) 0)
(const_int 1 [0x1]))) 9 {addsi3} (nil)
(expr_list:REG_DEAD (reg/v:HI 879)
(nil)))
As you can see is, what happens is that the addsi insn 2219 in 22.lreg
(we only have addsi, not addhi), is getting a reload, but what happens
to be a HI, is now fully SI resulting into a 32 bit load later in the
assembly.
Question: is it possible to say, is this a bug or a feature?
Thanks, Regards.
Hendrik Greving