I was analyzing an issue for avr target (gcc-4.7.2).
Issue is that already clobbered register is used after the transformation
in post reload pass.
insns after reload pass:
set (reg:HI r24
(const:HI (plus:HI (symbol_ref:HI ("array"))
(const_int 4))
))
...
parallel set (reg:HI r14
(and:HI (reg:HI r14)
(const_int 3)))
clobber:QI r25
...
set (reg:HI r28
(const:HI (plus:HI (symbol_ref:HI ("array"))
(const_int 4))
))
After post reload pass, insn-3 transformed as follows:
set (reg:HI r28
reg:HI r24)
this transformation happened in reload_cse_move2add function.
Since r25 is clobbered in insn-2, above transformation (r28/29 <= r24/25)
become incorrect.