This is the mail archive of the
gcc@gcc.gnu.org
mailing list for the GCC project.
PR53914, rs6000 constraints and reload queries
- From: Alan Modra <amodra at gmail dot com>
- To: gcc at gcc dot gnu dot org
- Cc: dje dot gcc at gmail dot com, bergner at vnet dot ibm dot com, mrmeissn at us dot ibm dot com, uweigand at de dot ibm dot com
- Date: Wed, 18 Jul 2012 01:04:11 +0930
- Subject: PR53914, rs6000 constraints and reload queries
This email is a result of delving into
https://bugzilla.redhat.com/show_bug.cgi?id=837630 an ICE when
building powerpc-linux gcc 4.7.1 with -fprofile-generate. I'm asking
for corrections/advice/guidance from anyone with a good working
knowledge of reload!
The ICE is
combine.c:5318:1: error: insn does not satisfy its constraints:
(insn 4211 1484 1493 140 (set (mem/c:DI (plus:SI (reg/f:SI 19 19 [2736])
(const_int 32760 [0x7ff8])) [3 __gcov0.subst+816 S8 A64])
(reg:DI 6 6)) 399 {*movdi_internal32}
(nil))
If you consider this insn, it's actually good and should result in
stw 6,0x7ff8(19); stw 7,0x7ffc(19)
However, the "o" constraint rejects any offset >= 0x7ff4 due to
rs6000_mode_dependent_address. This particular problem has been known
for a long time, but that's not the only problem with "o" (and also
the rs6000 "Y" constraint, a variant of "o"). A more subtle
requirement on constraints is that the relevant ones must match the
output of legitimize_reload_address. rs6000_legitimize_reload_address
for example can generate an address like
(plus (plus (reg x) (const_int high_part)) (const_int low_part))
for stack slots and other large offset mems, pushing a reload for the
innermost "plus". So the final address will just be
(plus (reg y) (const_int low_part))
an offset address, but the constraint sees that nested "plus" rtl.
Also, strict_memory_address_addr_space_p must *not* match the output
of legitimize_reload_address when reloads have been pushed. The
reason for this is that reload often makes multiple passes over insns,
and the modifications done by legitimize_reload_address are permanent.
On the second or subsequent passes, if that "(plus (plus ..))" address
is seen as valid, reload will leave it that way. So you lose the
reloads and are left with an invalid insn.
First reload question: Is any of the above para incorrect?
Now the "o" constraint is offsettable_nonstrict_memref_p, and the
rs6000 "Y" constraint currently calls memory_operand. The validity of
rs6000 offset addresses thus depends on the result of
rs6000_legitimate_address_p with "strict" false. Which means that
rs6000_legitimate_address_p ought to accept those "(plus (plus ..))"
addresses with "strict" false and reload_in_progress. However, when I
tried that I ran into a gfortran testsuite segfault, cray_pointers_2.
Investigating that showed (set (mem:DI (pre_inc:SI 241)) (reg:DI 488))
was getting two reload insns for pseudo 241 reversed. I saw
(set (reg:SI 8) (mem:SI (plus:SI (reg:SI 7) (const_int -16346))))
(set (reg:SI 7) (plus:SI (reg:SI 1) (const_int 65536)))
Something to do with special treatment of pre_inc somewhere, no doubt,
and probably not too hard to fix, but at that point I decided I'd had
enough of reload.
So instead this patch removes the unnecessary memory_operand call from
the "Y" constraint, and replaces most uses of the "o" constraint with
either "Y" or "wY", a new constraint like "Y" but for fprs. The idea
is that these constraints handle mems for just one type of reg, gpr or
fpr, and thus can properly handle the offset restrictions. "o" can't
do this because the mem mode does *not* guarantee the register type
being loaded/stored. For example, a DImode mem may well be used to
load/store a floating point reg, and a DFmode mem can be used with a
gpr (or two). This type of problem also makes it impossible to write
a version of rs6000_legitimate_offset_address_p that both allows ideal
code and is strict enough to be used with simple "m" constraints for
anything but 32-bit or smaller modes. What I've done there is to
relax rs6000_legitimate_offset_address_p when used in operand
predicates or by most mem validation functions, assuming best-case
regs are going to be used. If worst-case regs are used, then the
constraints ought to sort that out, forcing reloads.
(This change is probably incomplete. I think I need to write more
secondary reload patterns. For example to handle a 64-bit mem with
an offset in the range 7ffc to 7fff used with 32-bit gprs.
Second reload question: Am I correct in assuming this is needed? The
case I'm thinking of is a pseudo that doesn't get a hard reg but has a
non-stack mem equiv.)
I've also made a few other cleanups. Actually bootstraps with no
regressions on powerpc64-linux but at this stage I'm not looking to
apply. Testcases attached, one of which ICEs on current mainline.
PR target/53914
* config/rs6000/constraints.md (Y): Use mem_operand_gpr.
(wY): New constraint using mem_operand_fpr.
* config/rs6000/predicates.md (word_offset_memref_operand): Delete.
Adjust all rs6000_legitimate_offset_address_p calls.
* config/rs6000/rs6000-protos.h (mem_operand_gpr): Declare.
(mem_operand_fpr): Declare.
(rs6000_legitimate_offset_address_p): Update prototype.
(rs6000_offsettable_memref_p): Delete.
* config/rs6000/rs6000.c (mem_operand_gpr): New function.
(mem_operand_fpr): Likewise.
(rs6000_legitimate_offset_address_p): Add worst_case param. When
not worst_case assume class of regs with least restrictive offsets.
Adjust all calls.
(legitimate_lo_sum_address_p): Simplify register mode tests.
(rs6000_legitimize_address): Likewise. Assume best case offset
addressing. Combine ELF and MACHO lo_sum code.
(rs6000_mode_dependent_address): Correct offset addressing limits.
(rs6000_offsettable_memref_p): Make static, add reg_mode param.
Use reg_mode to help rs6000_legitimate_offset_address_p.
(rs6000_secondary_reload): Delete redundant code handling old tocrefs.
(rs6000_split_multireg_move): Adjust rs6000_offsettable_memref_p calls.
* config/rs6000/rs6000.md (movdf_hardfloat32): Use 'Y' constraint
for gpr load/store. Move r->r later.
(movdf_softfloat32): Likewise.
(movdi_mfpgpr, movdi_internal64, movti_ppc64): Likewise. Put r->Y
before Y->r.
(movdi_internal32): Likewise. Also disparage fprs.
(movtf_internal): Use 'wY' for fpr load/store.
(extenddftf2_internal): Use 'wY' and 'Y' for store.
(movti_power, movti_string): Use 'Y' for gpr load/store.
(stack_protect_setdi, stack_protect_testdi): Likewise.
Index: gcc/config/rs6000/constraints.md
===================================================================
--- gcc/config/rs6000/constraints.md (revision 189420)
+++ gcc/config/rs6000/constraints.md (working copy)
@@ -150,9 +150,15 @@ to use @samp{m} or @samp{es} in @code{asm} stateme
(match_test "GET_CODE (XEXP (op, 0)) == REG")))
(define_memory_constraint "Y"
- "Indexed or word-aligned displacement memory operand"
- (match_operand 0 "word_offset_memref_operand"))
+ "memory operand for 8 byte and 16 byte gpr load/store"
+ (and (match_code "mem")
+ (match_operand 0 "mem_operand_gpr")))
+(define_memory_constraint "wY"
+ "memory operand for 8 byte and 16 byte fpr load/store"
+ (and (match_code "mem")
+ (match_operand 0 "mem_operand_fpr")))
+
(define_memory_constraint "Z"
"Memory operand that is an indexed or indirect from a register (it is
usually better to use @samp{m} or @samp{es} in @code{asm} statements)"
Index: gcc/config/rs6000/predicates.md
===================================================================
--- gcc/config/rs6000/predicates.md (revision 189420)
+++ gcc/config/rs6000/predicates.md (working copy)
@@ -432,29 +432,6 @@
(and (match_operand 0 "memory_operand")
(match_test "offsettable_nonstrict_memref_p (op)")))
-;; Return 1 if the operand is a memory operand with an address divisible by 4
-(define_predicate "word_offset_memref_operand"
- (match_operand 0 "memory_operand")
-{
- /* Address inside MEM. */
- op = XEXP (op, 0);
-
- /* Extract address from auto-inc/dec. */
- if (GET_CODE (op) == PRE_INC
- || GET_CODE (op) == PRE_DEC)
- op = XEXP (op, 0);
- else if (GET_CODE (op) == PRE_MODIFY)
- op = XEXP (op, 1);
- else if (GET_CODE (op) == LO_SUM
- && GET_CODE (XEXP (op, 0)) == REG
- && GET_CODE (XEXP (op, 1)) == CONST)
- op = XEXP (XEXP (op, 1), 0);
-
- return (GET_CODE (op) != PLUS
- || GET_CODE (XEXP (op, 1)) != CONST_INT
- || INTVAL (XEXP (op, 1)) % 4 == 0);
-})
-
;; Return 1 if the operand is an indexed or indirect memory operand.
(define_predicate "indexed_or_indirect_operand"
(match_code "mem")
@@ -892,7 +869,8 @@
return input_operand (op, mode);
})
-;; Return true if OP is an invalid SUBREG operation on the e500.
+;; Return true if OP is a non-immediate operand and not an invalid
+;; SUBREG operation on the e500.
(define_predicate "rs6000_nonimmediate_operand"
(match_code "reg,subreg,mem")
{
@@ -1325,7 +1303,7 @@
if (base_regno == 0)
return 0;
}
- else if (rs6000_legitimate_offset_address_p (SImode, src_addr, 0))
+ else if (rs6000_legitimate_offset_address_p (SImode, src_addr, false, false))
{
offset = INTVAL (XEXP (src_addr, 1));
base_regno = REGNO (XEXP (src_addr, 0));
@@ -1353,7 +1331,7 @@
newoffset = 0;
addr_reg = newaddr;
}
- else if (rs6000_legitimate_offset_address_p (SImode, newaddr, 0))
+ else if (rs6000_legitimate_offset_address_p (SImode, newaddr, false, false))
{
addr_reg = XEXP (newaddr, 0);
newoffset = INTVAL (XEXP (newaddr, 1));
@@ -1400,7 +1378,7 @@
if (base_regno == 0)
return 0;
}
- else if (rs6000_legitimate_offset_address_p (SImode, dest_addr, 0))
+ else if (rs6000_legitimate_offset_address_p (SImode, dest_addr, false, false))
{
offset = INTVAL (XEXP (dest_addr, 1));
base_regno = REGNO (XEXP (dest_addr, 0));
@@ -1428,7 +1406,7 @@
newoffset = 0;
addr_reg = newaddr;
}
- else if (rs6000_legitimate_offset_address_p (SImode, newaddr, 0))
+ else if (rs6000_legitimate_offset_address_p (SImode, newaddr, false, false))
{
addr_reg = XEXP (newaddr, 0);
newoffset = INTVAL (XEXP (newaddr, 1));
Index: gcc/config/rs6000/rs6000-protos.h
===================================================================
--- gcc/config/rs6000/rs6000-protos.h (revision 189420)
+++ gcc/config/rs6000/rs6000-protos.h (working copy)
@@ -38,6 +38,8 @@ extern bool macho_lo_sum_memory_operand (rtx, enum
extern int num_insns_constant (rtx, enum machine_mode);
extern int num_insns_constant_wide (HOST_WIDE_INT);
extern int small_data_operand (rtx, enum machine_mode);
+extern bool mem_operand_gpr (rtx, enum machine_mode);
+extern bool mem_operand_fpr (rtx, enum machine_mode);
extern bool toc_relative_expr_p (const_rtx, bool);
extern bool invalid_e500_subreg (rtx, enum machine_mode);
extern void validate_condition_mode (enum rtx_code, enum machine_mode);
@@ -121,9 +123,9 @@ extern void rs6000_emit_move (rtx, rtx, enum machi
extern rtx rs6000_secondary_memory_needed_rtx (enum machine_mode);
extern rtx (*rs6000_legitimize_reload_address_ptr) (rtx, enum machine_mode,
int, int, int, int *);
-extern bool rs6000_legitimate_offset_address_p (enum machine_mode, rtx, int);
+extern bool rs6000_legitimate_offset_address_p (enum machine_mode, rtx,
+ bool, bool);
extern rtx rs6000_find_base_term (rtx);
-extern bool rs6000_offsettable_memref_p (rtx);
extern rtx rs6000_return_addr (int, rtx);
extern void rs6000_output_symbol_ref (FILE*, rtx);
extern HOST_WIDE_INT rs6000_initial_elimination_offset (int, int);
Index: gcc/config/rs6000/rs6000.c
===================================================================
--- gcc/config/rs6000/rs6000.c (revision 189420)
+++ gcc/config/rs6000/rs6000.c (working copy)
@@ -4956,6 +4956,78 @@ gpr_or_gpr_p (rtx op0, rtx op1)
|| (REG_P (op1) && INT_REGNO_P (REGNO (op1))));
}
+/* Return true if the MEM operand is a memory operand suitable for use
+ with a (full width, possibly multiple) gpr load/store. On
+ powerpc64 this means the offset must be divisible by 4.
+ Implements 'Y' constraint.
+
+ Accept direct, indexed, offset, lo_sum and tocref. Since this is
+ a constraint function we know the operand has satisfied a suitable
+ memory predicate. Also accept some odd rtl generated by reload
+ (see rs6000_legitimize_reload_address for various forms). It is
+ important that reload rtl be accepted by appropriate constraints
+ but not by the operand predicate. */
+
+bool
+mem_operand_gpr (rtx op, enum machine_mode mode)
+{
+ unsigned HOST_WIDE_INT offset;
+ unsigned int extra;
+
+ /* Address inside MEM. */
+ op = XEXP (op, 0);
+
+ /* Extract address from auto-inc/dec. */
+ if (GET_CODE (op) == PRE_INC
+ || GET_CODE (op) == PRE_DEC)
+ op = XEXP (op, 0);
+ else if (GET_CODE (op) == PRE_MODIFY)
+ op = XEXP (op, 1);
+
+ if (GET_CODE (op) != PLUS
+ || GET_CODE (XEXP (op, 1)) != CONST_INT)
+ return true;
+
+ offset = INTVAL (XEXP (op, 1));
+ if (TARGET_POWERPC64 && offset % 4 != 0)
+ return false;
+ extra = GET_MODE_SIZE (mode) - UNITS_PER_WORD;
+ if ((int) extra < 0)
+ extra = 0;
+ return offset + 0x8000 < 0x10000 - extra;
+}
+
+/* Return true if the MEM operand is a memory operand suitable for use
+ with a (possibly multiple) fpr load/store.
+ Implements 'wY' constraint. */
+
+bool
+mem_operand_fpr (rtx op, enum machine_mode mode)
+{
+ unsigned HOST_WIDE_INT offset;
+ unsigned int extra;
+
+ /* Address inside MEM. */
+ op = XEXP (op, 0);
+
+ /* Extract address from auto-inc/dec. */
+ if (GET_CODE (op) == PRE_INC
+ || GET_CODE (op) == PRE_DEC)
+ op = XEXP (op, 0);
+ else if (GET_CODE (op) == PRE_MODIFY)
+ op = XEXP (op, 1);
+
+ if (GET_CODE (op) != PLUS
+ || GET_CODE (XEXP (op, 1)) != CONST_INT)
+ return true;
+
+ offset = INTVAL (XEXP (op, 1));
+ extra = GET_MODE_SIZE (mode) - 8;
+ if ((int) extra < 0)
+ extra = 0;
+ return offset + 0x8000 < 0x10000 - extra;
+}
+
/* Subroutines of rs6000_legitimize_address and rs6000_legitimate_address_p. */
@@ -5173,13 +5245,15 @@ legitimate_small_data_p (enum machine_mode mode, r
#define SPE_CONST_OFFSET_OK(x) (((x) & ~0xf8) == 0)
bool
-rs6000_legitimate_offset_address_p (enum machine_mode mode, rtx x, int strict)
+rs6000_legitimate_offset_address_p (enum machine_mode mode, rtx x,
+ bool strict, bool worst_case)
{
- unsigned HOST_WIDE_INT offset, extra;
+ unsigned HOST_WIDE_INT offset;
+ unsigned int extra;
if (GET_CODE (x) != PLUS)
return false;
- if (GET_CODE (XEXP (x, 0)) != REG)
+ if (!REG_P (XEXP (x, 0)))
return false;
if (!INT_REG_OK_FOR_BASE_P (XEXP (x, 0), strict))
return false;
@@ -5202,14 +5276,6 @@ bool
return SPE_CONST_OFFSET_OK (offset);
case DFmode:
- if (TARGET_E500_DOUBLE)
- return SPE_CONST_OFFSET_OK (offset);
-
- /* If we are using VSX scalar loads, restrict ourselves to reg+reg
- addressing. */
- if (VECTOR_MEM_VSX_P (DFmode))
- return false;
-
case DDmode:
case DImode:
/* On e500v2, we may have:
@@ -5220,25 +5286,33 @@ bool
if (TARGET_E500_DOUBLE)
return SPE_CONST_OFFSET_OK (offset);
- if (mode == DFmode || mode == DDmode || !TARGET_POWERPC64)
+ /* If we are using VSX scalar loads, restrict ourselves to reg+reg
+ addressing. */
+ if (mode == DFmode && VECTOR_MEM_VSX_P (DFmode))
+ return false;
+
+ if (!worst_case)
+ break;
+ if (!TARGET_POWERPC64)
extra = 4;
else if (offset & 3)
return false;
break;
case TFmode:
+ case TDmode:
+ case TImode:
if (TARGET_E500_DOUBLE)
return (SPE_CONST_OFFSET_OK (offset)
&& SPE_CONST_OFFSET_OK (offset + 8));
- case TDmode:
- case TImode:
- if (mode == TFmode || mode == TDmode || !TARGET_POWERPC64)
+ extra = 8;
+ if (!worst_case)
+ break;
+ if (!TARGET_POWERPC64)
extra = 12;
else if (offset & 3)
return false;
- else
- extra = 8;
break;
default:
@@ -5318,9 +5392,7 @@ legitimate_lo_sum_address_p (enum machine_mode mod
if (!INT_REG_OK_FOR_BASE_P (XEXP (x, 0), strict))
return false;
/* Restrict addressing for DI because of our SUBREG hackery. */
- if (TARGET_E500_DOUBLE && (mode == DFmode || mode == TFmode
- || mode == DDmode || mode == TDmode
- || mode == DImode))
+ if (TARGET_E500_DOUBLE && GET_MODE_SIZE (mode) > UNITS_PER_WORD)
return false;
x = XEXP (x, 1);
@@ -5332,10 +5404,10 @@ legitimate_lo_sum_address_p (enum machine_mode mod
return false;
if (GET_MODE_NUNITS (mode) != 1)
return false;
- if (GET_MODE_BITSIZE (mode) > 64
- || (GET_MODE_BITSIZE (mode) > 32 && !TARGET_POWERPC64
- && !(TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_DOUBLE_FLOAT
- && (mode == DFmode || mode == DDmode))))
+ if (GET_MODE_SIZE (mode) > UNITS_PER_WORD
+ && !(/* ??? Assume floating point reg based on mode? */
+ TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_DOUBLE_FLOAT
+ && (mode == DFmode || mode == DDmode)))
return false;
return CONSTANT_P (x);
@@ -5370,7 +5442,7 @@ static rtx
rs6000_legitimize_address (rtx x, rtx oldx ATTRIBUTE_UNUSED,
enum machine_mode mode)
{
- unsigned int extra = 0;
+ unsigned int extra;
if (!reg_offset_addressing_ok_p (mode))
{
@@ -5397,22 +5469,18 @@ rs6000_legitimize_address (rtx x, rtx oldx ATTRIBU
return rs6000_legitimize_tls_address (x, model);
}
+ extra = 0;
switch (mode)
{
- case DFmode:
- case DDmode:
- extra = 4;
- break;
- case DImode:
- if (!TARGET_POWERPC64)
- extra = 4;
- break;
case TFmode:
case TDmode:
- extra = 12;
- break;
case TImode:
- extra = TARGET_POWERPC64 ? 8 : 12;
+ /* As in legitimate_offset_address_p we do not assume
+ worst-case. The mode here is just a hint as to the registers
+ used. A TImode is usually in gprs, but may actually be in
+ fprs. Leave worst-case scenario for reload to handle via
+ insn constraints. */
+ extra = 8;
break;
default:
break;
@@ -5423,13 +5491,8 @@ rs6000_legitimize_address (rtx x, rtx oldx ATTRIBU
&& GET_CODE (XEXP (x, 1)) == CONST_INT
&& ((unsigned HOST_WIDE_INT) (INTVAL (XEXP (x, 1)) + 0x8000)
>= 0x10000 - extra)
- && !((TARGET_POWERPC64
- && (mode == DImode || mode == TImode)
- && (INTVAL (XEXP (x, 1)) & 3) != 0)
- || SPE_VECTOR_MODE (mode)
- || (TARGET_E500_DOUBLE && (mode == DFmode || mode == TFmode
- || mode == DImode || mode == DDmode
- || mode == TDmode))))
+ && !(SPE_VECTOR_MODE (mode)
+ || (TARGET_E500_DOUBLE && GET_MODE_SIZE (mode) > UNITS_PER_WORD)))
{
HOST_WIDE_INT high_int, low_int;
rtx sum;
@@ -5445,23 +5508,17 @@ rs6000_legitimize_address (rtx x, rtx oldx ATTRIBU
&& GET_CODE (XEXP (x, 0)) == REG
&& GET_CODE (XEXP (x, 1)) != CONST_INT
&& GET_MODE_NUNITS (mode) == 1
- && ((TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_DOUBLE_FLOAT)
- || TARGET_POWERPC64
- || ((mode != DImode && mode != DFmode && mode != DDmode)
- || (TARGET_E500_DOUBLE && mode != DDmode)))
- && (TARGET_POWERPC64 || mode != DImode)
- && !avoiding_indexed_address_p (mode)
- && mode != TImode
- && mode != TFmode
- && mode != TDmode)
+ && (GET_MODE_SIZE (mode) <= UNITS_PER_WORD
+ || (/* ??? Assume floating point reg based on mode? */
+ (TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_DOUBLE_FLOAT)
+ && (mode == DFmode || mode == DDmode)))
+ && !avoiding_indexed_address_p (mode))
{
return gen_rtx_PLUS (Pmode, XEXP (x, 0),
force_reg (Pmode, force_operand (XEXP (x, 1), 0)));
}
else if (SPE_VECTOR_MODE (mode)
- || (TARGET_E500_DOUBLE && (mode == DFmode || mode == TFmode
- || mode == DDmode || mode == TDmode
- || mode == DImode)))
+ || (TARGET_E500_DOUBLE && GET_MODE_SIZE (mode) > UNITS_PER_WORD))
{
if (mode == DImode)
return x;
@@ -5494,7 +5551,11 @@ rs6000_legitimize_address (rtx x, rtx oldx ATTRIBU
return force_reg (Pmode, x);
}
- else if (TARGET_ELF
+ else if ((TARGET_ELF
+#if TARGET_MACHO
+ || !MACHO_DYNAMIC_NO_PIC_P
+#endif
+ )
&& TARGET_32BIT
&& TARGET_NO_TOC
&& ! flag_pic
@@ -5502,32 +5563,18 @@ rs6000_legitimize_address (rtx x, rtx oldx ATTRIBU
&& GET_CODE (x) != CONST_DOUBLE
&& CONSTANT_P (x)
&& GET_MODE_NUNITS (mode) == 1
- && (GET_MODE_BITSIZE (mode) <= 32
- || ((TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_DOUBLE_FLOAT)
+ && (GET_MODE_SIZE (mode) <= UNITS_PER_WORD
+ || (/* ??? Assume floating point reg based on mode? */
+ (TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_DOUBLE_FLOAT)
&& (mode == DFmode || mode == DDmode))))
{
rtx reg = gen_reg_rtx (Pmode);
- emit_insn (gen_elf_high (reg, x));
+ if (TARGET_ELF)
+ emit_insn (gen_elf_high (reg, x));
+ else
+ emit_insn (gen_macho_high (reg, x));
return gen_rtx_LO_SUM (Pmode, reg, x);
}
- else if (TARGET_MACHO && TARGET_32BIT && TARGET_NO_TOC
- && ! flag_pic
-#if TARGET_MACHO
- && ! MACHO_DYNAMIC_NO_PIC_P
-#endif
- && GET_CODE (x) != CONST_INT
- && GET_CODE (x) != CONST_DOUBLE
- && CONSTANT_P (x)
- && GET_MODE_NUNITS (mode) == 1
- && ((TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_DOUBLE_FLOAT)
- || (mode != DFmode && mode != DDmode))
- && mode != DImode
- && mode != TImode)
- {
- rtx reg = gen_reg_rtx (Pmode);
- emit_insn (gen_macho_high (reg, x));
- return gen_rtx_LO_SUM (Pmode, reg, x);
- }
else if (TARGET_TOC
&& GET_CODE (x) == SYMBOL_REF
&& constant_pool_expr_p (x)
@@ -6266,7 +6313,7 @@ rs6000_legitimate_address_p (enum machine_mode mod
|| XEXP (x, 0) == arg_pointer_rtx)
&& GET_CODE (XEXP (x, 1)) == CONST_INT)
return 1;
- if (rs6000_legitimate_offset_address_p (mode, x, reg_ok_strict))
+ if (rs6000_legitimate_offset_address_p (mode, x, reg_ok_strict, false))
return 1;
if (mode != TImode
&& mode != TFmode
@@ -6294,7 +6341,8 @@ rs6000_legitimate_address_p (enum machine_mode mod
&& (mode == DFmode || mode == DDmode || mode == DImode))
&& TARGET_UPDATE
&& legitimate_indirect_address_p (XEXP (x, 0), reg_ok_strict)
- && (rs6000_legitimate_offset_address_p (mode, XEXP (x, 1), reg_ok_strict)
+ && (rs6000_legitimate_offset_address_p (mode, XEXP (x, 1),
+ reg_ok_strict, false)
|| (!avoiding_indexed_address_p (mode)
&& legitimate_indexed_address_p (XEXP (x, 1), reg_ok_strict)))
&& rtx_equal_p (XEXP (XEXP (x, 1), 0), XEXP (x, 0)))
@@ -6358,7 +6406,7 @@ rs6000_mode_dependent_address (const_rtx addr)
&& GET_CODE (XEXP (addr, 1)) == CONST_INT)
{
unsigned HOST_WIDE_INT val = INTVAL (XEXP (addr, 1));
- return val + 12 + 0x8000 >= 0x10000;
+ return val + 0x8000 >= 0x10000 - (TARGET_POWERPC64 ? 8 : 12);
}
break;
@@ -6428,14 +6476,16 @@ rs6000_find_base_term (rtx op)
in 32-bit mode, that the recog predicate rejects. */
-bool
-rs6000_offsettable_memref_p (rtx op)
+static bool
+rs6000_offsettable_memref_p (rtx op, enum machine_mode reg_mode)
{
+ bool worst_case;
+
if (!MEM_P (op))
return false;
/* First mimic offsettable_memref_p. */
- if (offsettable_address_p (1, GET_MODE (op), XEXP (op, 0)))
+ if (offsettable_address_p (true, GET_MODE (op), XEXP (op, 0)))
return true;
/* offsettable_address_p invokes rs6000_mode_dependent_address, but
@@ -6443,8 +6493,13 @@ rs6000_find_base_term (rtx op)
reference and, therefore, assumes that it is the largest supported
mode (TFmode). As a consequence, legitimate offsettable memory
references are rejected. rs6000_legitimate_offset_address_p contains
- the correct logic for the PLUS case of rs6000_mode_dependent_address. */
- return rs6000_legitimate_offset_address_p (GET_MODE (op), XEXP (op, 0), 1);
+ the correct logic for the PLUS case of rs6000_mode_dependent_address,
+ at least with a little bit of help here given that we know the
+ actual registers used. */
+ worst_case = ((TARGET_POWERPC64 && GET_MODE_CLASS (reg_mode) == MODE_INT)
+ || GET_MODE_SIZE (reg_mode) == 4);
+ return rs6000_legitimate_offset_address_p (GET_MODE (op), XEXP (op, 0),
+ true, worst_case);
}
/* Change register usage conditional on target flags. */
@@ -13455,7 +13510,8 @@ rs6000_secondary_reload (bool in_p,
if (rclass == GENERAL_REGS || rclass == BASE_REGS)
{
if (!legitimate_indirect_address_p (addr, false)
- && !rs6000_legitimate_offset_address_p (TImode, addr, false))
+ && !rs6000_legitimate_offset_address_p (TImode, addr,
+ false, true))
{
sri->icode = icode;
/* account for splitting the loads, and converting the
@@ -13532,10 +13588,6 @@ rs6000_secondary_reload (bool in_p,
if (GET_CODE (addr) == PRE_MODIFY)
addr = XEXP (addr, 1);
- else if (GET_CODE (addr) == LO_SUM
- && GET_CODE (XEXP (addr, 0)) == REG
- && GET_CODE (XEXP (addr, 1)) == CONST)
- addr = XEXP (XEXP (addr, 1), 0);
if (GET_CODE (addr) == PLUS
&& GET_CODE (XEXP (addr, 1)) == CONST_INT
@@ -13639,8 +13691,9 @@ rs6000_secondary_reload_inner (rtx reg, rtx mem, r
}
if (GET_CODE (addr) == PLUS
- && (!rs6000_legitimate_offset_address_p (TImode, addr, false)
- || and_op2 != NULL_RTX))
+ && (and_op2 != NULL_RTX
+ || !rs6000_legitimate_offset_address_p (TImode, addr,
+ false, true)))
{
addr_op1 = XEXP (addr, 0);
addr_op2 = XEXP (addr, 1);
@@ -13672,7 +13725,8 @@ rs6000_secondary_reload_inner (rtx reg, rtx mem, r
scratch_or_premodify = scratch;
}
else if (!legitimate_indirect_address_p (addr, false)
- && !rs6000_legitimate_offset_address_p (TImode, addr, false))
+ && !rs6000_legitimate_offset_address_p (TImode, addr,
+ false, true))
{
if (TARGET_DEBUG_ADDR)
{
@@ -13731,7 +13785,7 @@ rs6000_secondary_reload_inner (rtx reg, rtx mem, r
&& GET_MODE_SIZE (mode) == 8
&& and_op2 == NULL_RTX
&& scratch_or_premodify == scratch
- && rs6000_legitimate_offset_address_p (mode, addr, false)))
+ && rs6000_legitimate_offset_address_p (mode, addr, false, false)))
;
else if (GET_CODE (addr) == PLUS)
@@ -16932,7 +16986,7 @@ rs6000_split_multireg_move (rtx dst, rtx src)
emit_insn (gen_add3_insn (breg, breg, delta_rtx));
src = replace_equiv_address (src, breg);
}
- else if (! rs6000_offsettable_memref_p (src))
+ else if (! rs6000_offsettable_memref_p (src, reg_mode))
{
if (GET_CODE (XEXP (src, 0)) == PRE_MODIFY)
{
@@ -16998,7 +17052,7 @@ rs6000_split_multireg_move (rtx dst, rtx src)
emit_insn (gen_add3_insn (breg, breg, delta_rtx));
dst = replace_equiv_address (dst, breg);
}
- else if (!rs6000_offsettable_memref_p (dst)
+ else if (!rs6000_offsettable_memref_p (dst, reg_mode)
&& GET_CODE (XEXP (dst, 0)) != LO_SUM)
{
if (GET_CODE (XEXP (dst, 0)) == PRE_MODIFY)
@@ -17036,7 +17090,7 @@ rs6000_split_multireg_move (rtx dst, rtx src)
}
}
else if (GET_CODE (XEXP (dst, 0)) != LO_SUM)
- gcc_assert (rs6000_offsettable_memref_p (dst));
+ gcc_assert (rs6000_offsettable_memref_p (dst, reg_mode));
}
for (i = 0; i < nregs; i++)
@@ -27874,7 +27928,7 @@ rs6000_allocate_stack_temp (enum machine_mode mode
if (!legitimate_indirect_address_p (addr, strict_p))
{
if (offsettable_p
- && !rs6000_legitimate_offset_address_p (mode, addr, strict_p))
+ && !rs6000_legitimate_offset_address_p (mode, addr, strict_p, true))
stack = replace_equiv_address (stack, copy_addr_to_reg (addr));
else if (reg_reg_p && !legitimate_indexed_address_p (addr, strict_p))
Index: gcc/config/rs6000/rs6000.md
===================================================================
--- gcc/config/rs6000/rs6000.md (revision 189420)
+++ gcc/config/rs6000/rs6000.md (working copy)
@@ -9666,8 +9666,8 @@
;; The "??" is a kludge until we can figure out a more reasonable way
;; of handling these non-offsettable values.
(define_insn "*movdf_hardfloat32"
- [(set (match_operand:DF 0 "nonimmediate_operand" "=!r,??r,m,ws,?wa,ws,?wa,Z,?Z,d,d,m,wa,!r,!r,!r")
- (match_operand:DF 1 "input_operand" "r,m,r,ws,wa,Z,Z,ws,wa,d,m,d,j,G,H,F"))]
+ [(set (match_operand:DF 0 "nonimmediate_operand" "=??r,Y,!r,ws,?wa,ws,?wa,Z,?Z,d,d,m,wa,!r,!r,!r")
+ (match_operand:DF 1 "input_operand" "Y,r,r,ws,wa,Z,Z,ws,wa,d,m,d,j,G,H,F"))]
"! TARGET_POWERPC64 && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_DOUBLE_FLOAT
&& (gpc_reg_operand (operands[0], DFmode)
|| gpc_reg_operand (operands[1], DFmode))"
@@ -9704,19 +9704,19 @@
return \"#\";
}
}"
- [(set_attr "type" "two,load,store,fp,fp,fpload,fpload,fpstore,fpstore,fp,fpload,fpstore,vecsimple,*,*,*")
- (set_attr "length" "8,16,16,4,4,4,4,4,4,4,4,4,4,8,12,16")])
+ [(set_attr "type" "load,store,two,fp,fp,fpload,fpload,fpstore,fpstore,fp,fpload,fpstore,vecsimple,*,*,*")
+ (set_attr "length" "16,16,8,4,4,4,4,4,4,4,4,4,4,8,12,16")])
(define_insn "*movdf_softfloat32"
- [(set (match_operand:DF 0 "nonimmediate_operand" "=r,r,m,r,r,r")
- (match_operand:DF 1 "input_operand" "r,m,r,G,H,F"))]
+ [(set (match_operand:DF 0 "nonimmediate_operand" "=r,Y,r,r,r,r")
+ (match_operand:DF 1 "input_operand" "Y,r,r,G,H,F"))]
"! TARGET_POWERPC64
&& ((TARGET_FPRS && TARGET_SINGLE_FLOAT)
|| TARGET_SOFT_FLOAT || TARGET_E500_SINGLE)
&& (gpc_reg_operand (operands[0], DFmode)
|| gpc_reg_operand (operands[1], DFmode))"
"#"
- [(set_attr "type" "two,load,store,*,*,*")
+ [(set_attr "type" "load,store,two,*,*,*")
(set_attr "length" "8,8,8,8,12,16")])
;; Reload patterns to support gpr load/store with misaligned mem.
@@ -9831,12 +9831,12 @@
"!TARGET_IEEEQUAD && TARGET_LONG_DOUBLE_128"
"{ rs6000_emit_move (operands[0], operands[1], TFmode); DONE; }")
-; It's important to list the o->f and f->o moves before f->f because
-; otherwise reload, given m->f, will try to pick f->f and reload it,
+; It's important to list the wY->d and d->wY moves before d->d because
+; otherwise reload, given m->d, will try to pick d->d and reload it,
; which doesn't make progress. Likewise r->Y must be before r->r.
(define_insn_and_split "*movtf_internal"
- [(set (match_operand:TF 0 "nonimmediate_operand" "=o,d,d,r,Y,r")
- (match_operand:TF 1 "input_operand" "d,o,d,YGHF,r,r"))]
+ [(set (match_operand:TF 0 "nonimmediate_operand" "=wY,d,d,r,Y,r")
+ (match_operand:TF 1 "input_operand" "d,wY,d,YGHF,r,r"))]
"!TARGET_IEEEQUAD
&& TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_LONG_DOUBLE_128
&& (gpc_reg_operand (operands[0], TFmode)
@@ -9890,9 +9890,9 @@
})
(define_insn_and_split "*extenddftf2_internal"
- [(set (match_operand:TF 0 "nonimmediate_operand" "=o,d,&d,r")
- (float_extend:TF (match_operand:DF 1 "input_operand" "dr,md,md,rmGHF")))
- (use (match_operand:DF 2 "zero_reg_mem_operand" "rd,m,d,n"))]
+ [(set (match_operand:TF 0 "nonimmediate_operand" "=wY,Y,d,&d,r")
+ (float_extend:TF (match_operand:DF 1 "input_operand" "d,r,md,md,rmGHF")))
+ (use (match_operand:DF 2 "zero_reg_mem_operand" "d,r,m,d,n"))]
"!TARGET_IEEEQUAD
&& TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_DOUBLE_FLOAT
&& TARGET_LONG_DOUBLE_128"
@@ -10145,11 +10145,11 @@
;; Next come the multi-word integer load and store and the load and store
;; multiple insns.
-; List r->r after r->"o<>", otherwise reload will try to reload a
-; non-offsettable address by using r->r which won't make progress.
+;; List r->r after r->Y, otherwise reload will try to reload a
+;; non-offsettable address by using r->r which won't make progress.
(define_insn "*movdi_internal32"
- [(set (match_operand:DI 0 "rs6000_nonimmediate_operand" "=o<>,r,r,*d,*d,m,r,?wa")
- (match_operand:DI 1 "input_operand" "r,r,m,d,m,d,IJKnGHF,O"))]
+ [(set (match_operand:DI 0 "rs6000_nonimmediate_operand" "=Y,r,r,*?d,*?d,?m,r,?wa")
+ (match_operand:DI 1 "input_operand" "r,Y,r,d,m,d,IJKnGHF,O"))]
"! TARGET_POWERPC64
&& (gpc_reg_operand (operands[0], DImode)
|| gpc_reg_operand (operands[1], DImode))"
@@ -10162,7 +10162,7 @@
stfd%U0%X0 %1,%0
#
xxlxor %x0,%x0,%x0"
- [(set_attr "type" "load,*,store,fp,fpload,fpstore,*,vecsimple")])
+ [(set_attr "type" "load,store,*,fp,fpload,fpstore,*,vecsimple")])
(define_split
[(set (match_operand:DI 0 "gpc_reg_operand" "")
@@ -10195,15 +10195,15 @@
{ rs6000_split_multireg_move (operands[0], operands[1]); DONE; })
(define_insn "*movdi_mfpgpr"
- [(set (match_operand:DI 0 "nonimmediate_operand" "=r,r,m,r,r,r,*d,*d,m,r,*h,*h,r,*d")
- (match_operand:DI 1 "input_operand" "r,m,r,I,L,nF,d,m,d,*h,r,0,*d,r"))]
+ [(set (match_operand:DI 0 "nonimmediate_operand" "=Y,r,r,r,r,r,*?d,*?d,?m,r,*h,*h,r,*?d")
+ (match_operand:DI 1 "input_operand" "r,Y,r,I,L,nF,d,m,d,*h,r,0,*d,r"))]
"TARGET_POWERPC64 && TARGET_MFPGPR && TARGET_HARD_FLOAT && TARGET_FPRS
&& (gpc_reg_operand (operands[0], DImode)
|| gpc_reg_operand (operands[1], DImode))"
"@
+ std%U0%X0 %1,%0
+ ld%U1%X1 %0,%1
mr %0,%1
- ld%U1%X1 %0,%1
- std%U0%X0 %1,%0
li %0,%1
lis %0,%v1
#
@@ -10215,19 +10215,19 @@
{cror 0,0,0|nop}
mftgpr %0,%1
mffgpr %0,%1"
- [(set_attr "type" "*,load,store,*,*,*,fp,fpload,fpstore,mfjmpr,mtjmpr,*,mftgpr,mffgpr")
+ [(set_attr "type" "store,load,*,*,*,*,fp,fpload,fpstore,mfjmpr,mtjmpr,*,mftgpr,mffgpr")
(set_attr "length" "4,4,4,4,4,20,4,4,4,4,4,4,4,4")])
(define_insn "*movdi_internal64"
- [(set (match_operand:DI 0 "nonimmediate_operand" "=r,r,m,r,r,r,*d,*d,m,r,*h,*h,?wa")
- (match_operand:DI 1 "input_operand" "r,m,r,I,L,nF,d,m,d,*h,r,0,O"))]
+ [(set (match_operand:DI 0 "nonimmediate_operand" "=Y,r,r,r,r,r,*?d,*?d,?m,r,*h,*h,?wa")
+ (match_operand:DI 1 "input_operand" "r,Y,r,I,L,nF,d,m,d,*h,r,0,O"))]
"TARGET_POWERPC64 && (!TARGET_MFPGPR || !TARGET_HARD_FLOAT || !TARGET_FPRS)
&& (gpc_reg_operand (operands[0], DImode)
|| gpc_reg_operand (operands[1], DImode))"
"@
+ std%U0%X0 %1,%0
+ ld%U1%X1 %0,%1
mr %0,%1
- ld%U1%X1 %0,%1
- std%U0%X0 %1,%0
li %0,%1
lis %0,%v1
#
@@ -10238,7 +10238,7 @@
mt%0 %1
{cror 0,0,0|nop}
xxlxor %x0,%x0,%x0"
- [(set_attr "type" "*,load,store,*,*,*,fp,fpload,fpstore,mfjmpr,mtjmpr,*,vecsimple")
+ [(set_attr "type" "store,load,*,*,*,*,fp,fpload,fpstore,mfjmpr,mtjmpr,*,vecsimple")
(set_attr "length" "4,4,4,4,4,20,4,4,4,4,4,4,4")])
;; immediate value valid for a single instruction hiding in a const_double
@@ -10313,8 +10313,8 @@
;; giving the SCRATCH mq.
(define_insn "*movti_power"
- [(set (match_operand:TI 0 "reg_or_mem_operand" "=Q,m,????r,????r,????r,r")
- (match_operand:TI 1 "input_operand" "r,r,r,Q,m,n"))
+ [(set (match_operand:TI 0 "reg_or_mem_operand" "=Q,Y,????r,????r,????r,r")
+ (match_operand:TI 1 "input_operand" "r,r,r,Q,Y,n"))
(clobber (match_scratch:SI 2 "=q,q#X,X,X,X,X"))]
"TARGET_POWER && ! TARGET_POWERPC64
&& (gpc_reg_operand (operands[0], TImode) || gpc_reg_operand (operands[1], TImode))"
@@ -10346,8 +10346,8 @@
[(set_attr "type" "store,store,*,load,load,*")])
(define_insn "*movti_string"
- [(set (match_operand:TI 0 "reg_or_mem_operand" "=Q,o<>,????r,????r,????r,r")
- (match_operand:TI 1 "input_operand" "r,r,r,Q,m,n"))]
+ [(set (match_operand:TI 0 "reg_or_mem_operand" "=Q,Y,????r,????r,????r,r")
+ (match_operand:TI 1 "input_operand" "r,r,r,Q,Y,n"))]
"! TARGET_POWER && ! TARGET_POWERPC64
&& (gpc_reg_operand (operands[0], TImode) || gpc_reg_operand (operands[1], TImode))"
"*
@@ -10380,13 +10380,13 @@
(const_string "conditional")))])
(define_insn "*movti_ppc64"
- [(set (match_operand:TI 0 "nonimmediate_operand" "=r,o<>,r")
- (match_operand:TI 1 "input_operand" "r,r,m"))]
+ [(set (match_operand:TI 0 "nonimmediate_operand" "=Y,r,r")
+ (match_operand:TI 1 "input_operand" "r,Y,r"))]
"(TARGET_POWERPC64 && (gpc_reg_operand (operands[0], TImode)
|| gpc_reg_operand (operands[1], TImode)))
&& VECTOR_MEM_NONE_P (TImode)"
"#"
- [(set_attr "type" "*,store,load")])
+ [(set_attr "type" "store,load,*")])
(define_split
[(set (match_operand:TI 0 "gpc_reg_operand" "")
@@ -13215,8 +13215,8 @@
(set_attr "length" "12")])
(define_insn "stack_protect_setdi"
- [(set (match_operand:DI 0 "memory_operand" "=m")
- (unspec:DI [(match_operand:DI 1 "memory_operand" "m")] UNSPEC_SP_SET))
+ [(set (match_operand:DI 0 "memory_operand" "=Y")
+ (unspec:DI [(match_operand:DI 1 "memory_operand" "Y")] UNSPEC_SP_SET))
(set (match_scratch:DI 2 "=&r") (const_int 0))]
"TARGET_64BIT"
"ld%U1%X1 %2,%1\;std%U0%X0 %2,%0\;{lil|li} %2,0"
@@ -13257,8 +13257,8 @@
(define_insn "stack_protect_testdi"
[(set (match_operand:CCEQ 0 "cc_reg_operand" "=x,?y")
- (unspec:CCEQ [(match_operand:DI 1 "memory_operand" "m,m")
- (match_operand:DI 2 "memory_operand" "m,m")]
+ (unspec:CCEQ [(match_operand:DI 1 "memory_operand" "Y,Y")
+ (match_operand:DI 2 "memory_operand" "Y,Y")]
UNSPEC_SP_TEST))
(set (match_scratch:DI 4 "=r,r") (const_int 0))
(clobber (match_scratch:DI 3 "=&r,&r"))]
--
Alan Modra
Australia Development Lab, IBM
void w1 (void *x, long long y) { *(long long *) (x + 32767) = y; }
void w2 (void *x, long long y) { *(long long *) (x + 32766) = y; }
void w3 (void *x, long long y) { *(long long *) (x + 32765) = y; }
void w4 (void *x, long long y) { *(long long *) (x + 32764) = y; }
void w5 (void *x, long long y) { *(long long *) (x + 32763) = y; }
void w6 (void *x, long long y) { *(long long *) (x + 32762) = y; }
void w7 (void *x, long long y) { *(long long *) (x + 32761) = y; }
void w8 (void *x, long long y) { *(long long *) (x + 32760) = y; }
void w9 (void *x, long long y) { *(long long *) (x + 32759) = y; }
void w10 (void *x, long long y) { *(long long *) (x + 32758) = y; }
void w11 (void *x, long long y) { *(long long *) (x + 32757) = y; }
void w12 (void *x, long long y) { *(long long *) (x + 32756) = y; }
void w13 (void *x, long long y) { *(long long *) (x + 32755) = y; }
void w14 (void *x, long long y) { *(long long *) (x + 32754) = y; }
void w15 (void *x, long long y) { *(long long *) (x + 32753) = y; }
void w16 (void *x, long long y) { *(long long *) (x + 32752) = y; }
void w17 (void *x, long long y) { *(long long *) (x + 32751) = y; }
void w18 (void *x, long long y) { *(long long *) (x + 32750) = y; }
void w19 (void *x, long long y) { *(long long *) (x + 32749) = y; }
void w20 (void *x, long long y) { *(long long *) (x + 32748) = y; }
long long r1 (void *x) { return *(long long *) (x + 32767); }
long long r2 (void *x) { return *(long long *) (x + 32766); }
long long r3 (void *x) { return *(long long *) (x + 32765); }
long long r4 (void *x) { return *(long long *) (x + 32764); }
long long r5 (void *x) { return *(long long *) (x + 32763); }
long long r6 (void *x) { return *(long long *) (x + 32762); }
long long r7 (void *x) { return *(long long *) (x + 32761); }
long long r8 (void *x) { return *(long long *) (x + 32760); }
long long r9 (void *x) { return *(long long *) (x + 32759); }
long long r10 (void *x) { return *(long long *) (x + 32758); }
long long r11 (void *x) { return *(long long *) (x + 32757); }
long long r12 (void *x) { return *(long long *) (x + 32756); }
long long r13 (void *x) { return *(long long *) (x + 32755); }
long long r14 (void *x) { return *(long long *) (x + 32754); }
long long r15 (void *x) { return *(long long *) (x + 32753); }
long long r16 (void *x) { return *(long long *) (x + 32752); }
long long r17 (void *x) { return *(long long *) (x + 32751); }
long long r18 (void *x) { return *(long long *) (x + 32750); }
long long r19 (void *x) { return *(long long *) (x + 32749); }
long long r20 (void *x) { return *(long long *) (x + 32748); }
void w1 (void *x, double y) { *(double *) (x + 32767) = y; }
void w2 (void *x, double y) { *(double *) (x + 32766) = y; }
void w3 (void *x, double y) { *(double *) (x + 32765) = y; }
void w4 (void *x, double y) { *(double *) (x + 32764) = y; }
void w5 (void *x, double y) { *(double *) (x + 32763) = y; }
void w6 (void *x, double y) { *(double *) (x + 32762) = y; }
void w7 (void *x, double y) { *(double *) (x + 32761) = y; }
void w8 (void *x, double y) { *(double *) (x + 32760) = y; }
void w9 (void *x, double y) { *(double *) (x + 32759) = y; }
void w10 (void *x, double y) { *(double *) (x + 32758) = y; }
void w11 (void *x, double y) { *(double *) (x + 32757) = y; }
void w12 (void *x, double y) { *(double *) (x + 32756) = y; }
void w13 (void *x, double y) { *(double *) (x + 32755) = y; }
void w14 (void *x, double y) { *(double *) (x + 32754) = y; }
void w15 (void *x, double y) { *(double *) (x + 32753) = y; }
void w16 (void *x, double y) { *(double *) (x + 32752) = y; }
void w17 (void *x, double y) { *(double *) (x + 32751) = y; }
void w18 (void *x, double y) { *(double *) (x + 32750) = y; }
void w19 (void *x, double y) { *(double *) (x + 32749) = y; }
void w20 (void *x, double y) { *(double *) (x + 32748) = y; }
double r1 (void *x) { return *(double *) (x + 32767); }
double r2 (void *x) { return *(double *) (x + 32766); }
double r3 (void *x) { return *(double *) (x + 32765); }
double r4 (void *x) { return *(double *) (x + 32764); }
double r5 (void *x) { return *(double *) (x + 32763); }
double r6 (void *x) { return *(double *) (x + 32762); }
double r7 (void *x) { return *(double *) (x + 32761); }
double r8 (void *x) { return *(double *) (x + 32760); }
double r9 (void *x) { return *(double *) (x + 32759); }
double r10 (void *x) { return *(double *) (x + 32758); }
double r11 (void *x) { return *(double *) (x + 32757); }
double r12 (void *x) { return *(double *) (x + 32756); }
double r13 (void *x) { return *(double *) (x + 32755); }
double r14 (void *x) { return *(double *) (x + 32754); }
double r15 (void *x) { return *(double *) (x + 32753); }
double r16 (void *x) { return *(double *) (x + 32752); }
double r17 (void *x) { return *(double *) (x + 32751); }
double r18 (void *x) { return *(double *) (x + 32750); }
double r19 (void *x) { return *(double *) (x + 32749); }
double r20 (void *x) { return *(double *) (x + 32748); }
typedef int TImode __attribute__ ((mode (TI)));
void w1 (void *x, TImode y) { *(TImode *) (x + 32767) = y; }
void w2 (void *x, TImode y) { *(TImode *) (x + 32766) = y; }
void w3 (void *x, TImode y) { *(TImode *) (x + 32765) = y; }
void w4 (void *x, TImode y) { *(TImode *) (x + 32764) = y; }
void w5 (void *x, TImode y) { *(TImode *) (x + 32763) = y; }
void w6 (void *x, TImode y) { *(TImode *) (x + 32762) = y; }
void w7 (void *x, TImode y) { *(TImode *) (x + 32761) = y; }
void w8 (void *x, TImode y) { *(TImode *) (x + 32760) = y; }
void w9 (void *x, TImode y) { *(TImode *) (x + 32759) = y; }
void w10 (void *x, TImode y) { *(TImode *) (x + 32758) = y; }
void w11 (void *x, TImode y) { *(TImode *) (x + 32757) = y; }
void w12 (void *x, TImode y) { *(TImode *) (x + 32756) = y; }
void w13 (void *x, TImode y) { *(TImode *) (x + 32755) = y; }
void w14 (void *x, TImode y) { *(TImode *) (x + 32754) = y; }
void w15 (void *x, TImode y) { *(TImode *) (x + 32753) = y; }
void w16 (void *x, TImode y) { *(TImode *) (x + 32752) = y; }
void w17 (void *x, TImode y) { *(TImode *) (x + 32751) = y; }
void w18 (void *x, TImode y) { *(TImode *) (x + 32750) = y; }
void w19 (void *x, TImode y) { *(TImode *) (x + 32749) = y; }
void w20 (void *x, TImode y) { *(TImode *) (x + 32748) = y; }
TImode r1 (void *x) { return *(TImode *) (x + 32767); }
TImode r2 (void *x) { return *(TImode *) (x + 32766); }
TImode r3 (void *x) { return *(TImode *) (x + 32765); }
TImode r4 (void *x) { return *(TImode *) (x + 32764); }
TImode r5 (void *x) { return *(TImode *) (x + 32763); }
TImode r6 (void *x) { return *(TImode *) (x + 32762); }
TImode r7 (void *x) { return *(TImode *) (x + 32761); }
TImode r8 (void *x) { return *(TImode *) (x + 32760); }
TImode r9 (void *x) { return *(TImode *) (x + 32759); }
TImode r10 (void *x) { return *(TImode *) (x + 32758); }
TImode r11 (void *x) { return *(TImode *) (x + 32757); }
TImode r12 (void *x) { return *(TImode *) (x + 32756); }
TImode r13 (void *x) { return *(TImode *) (x + 32755); }
TImode r14 (void *x) { return *(TImode *) (x + 32754); }
TImode r15 (void *x) { return *(TImode *) (x + 32753); }
TImode r16 (void *x) { return *(TImode *) (x + 32752); }
TImode r17 (void *x) { return *(TImode *) (x + 32751); }
TImode r18 (void *x) { return *(TImode *) (x + 32750); }
TImode r19 (void *x) { return *(TImode *) (x + 32749); }
TImode r20 (void *x) { return *(TImode *) (x + 32748); }
typedef float TFmode __attribute__ ((mode (TF)));
void w1 (void *x, TFmode y) { *(TFmode *) (x + 32767) = y; }
void w2 (void *x, TFmode y) { *(TFmode *) (x + 32766) = y; }
void w3 (void *x, TFmode y) { *(TFmode *) (x + 32765) = y; }
void w4 (void *x, TFmode y) { *(TFmode *) (x + 32764) = y; }
void w5 (void *x, TFmode y) { *(TFmode *) (x + 32763) = y; }
void w6 (void *x, TFmode y) { *(TFmode *) (x + 32762) = y; }
void w7 (void *x, TFmode y) { *(TFmode *) (x + 32761) = y; }
void w8 (void *x, TFmode y) { *(TFmode *) (x + 32760) = y; }
void w9 (void *x, TFmode y) { *(TFmode *) (x + 32759) = y; }
void w10 (void *x, TFmode y) { *(TFmode *) (x + 32758) = y; }
void w11 (void *x, TFmode y) { *(TFmode *) (x + 32757) = y; }
void w12 (void *x, TFmode y) { *(TFmode *) (x + 32756) = y; }
void w13 (void *x, TFmode y) { *(TFmode *) (x + 32755) = y; }
void w14 (void *x, TFmode y) { *(TFmode *) (x + 32754) = y; }
void w15 (void *x, TFmode y) { *(TFmode *) (x + 32753) = y; }
void w16 (void *x, TFmode y) { *(TFmode *) (x + 32752) = y; }
void w17 (void *x, TFmode y) { *(TFmode *) (x + 32751) = y; }
void w18 (void *x, TFmode y) { *(TFmode *) (x + 32750) = y; }
void w19 (void *x, TFmode y) { *(TFmode *) (x + 32749) = y; }
void w20 (void *x, TFmode y) { *(TFmode *) (x + 32748) = y; }
TFmode r1 (void *x) { return *(TFmode *) (x + 32767); }
TFmode r2 (void *x) { return *(TFmode *) (x + 32766); }
TFmode r3 (void *x) { return *(TFmode *) (x + 32765); }
TFmode r4 (void *x) { return *(TFmode *) (x + 32764); }
TFmode r5 (void *x) { return *(TFmode *) (x + 32763); }
TFmode r6 (void *x) { return *(TFmode *) (x + 32762); }
TFmode r7 (void *x) { return *(TFmode *) (x + 32761); }
TFmode r8 (void *x) { return *(TFmode *) (x + 32760); }
TFmode r9 (void *x) { return *(TFmode *) (x + 32759); }
TFmode r10 (void *x) { return *(TFmode *) (x + 32758); }
TFmode r11 (void *x) { return *(TFmode *) (x + 32757); }
TFmode r12 (void *x) { return *(TFmode *) (x + 32756); }
TFmode r13 (void *x) { return *(TFmode *) (x + 32755); }
TFmode r14 (void *x) { return *(TFmode *) (x + 32754); }
TFmode r15 (void *x) { return *(TFmode *) (x + 32753); }
TFmode r16 (void *x) { return *(TFmode *) (x + 32752); }
TFmode r17 (void *x) { return *(TFmode *) (x + 32751); }
TFmode r18 (void *x) { return *(TFmode *) (x + 32750); }
TFmode r19 (void *x) { return *(TFmode *) (x + 32749); }
TFmode r20 (void *x) { return *(TFmode *) (x + 32748); }