Re: Paradoxical subreg reload issue

[Eric Botcazou <ebotcazou at adacore dot com>]

> I have an issue (gcc 4.6.3, private bacakend) when reloading operands of
> this insn:
> (set (subreg:SI (reg:QI 21 [ iftmp.1 ]) 0)
>      (lshiftrt:SI (reg/v:SI 24 [ w ]) (const_int 31 [0x1f]))
>
> The register 21 is reloaded into
> (reg:QI 0 r0 [orig:21 iftmp.1 ] [21]), which is a HI-wide hw register.
> Since it is a BIG_ENDIAN target, the SI subreg regno is then -1.
>
> Note that word_mode is SImode, whereas the class r0 belongs to is
> HI-wide. I don't know if this matters when reloading.
>
> I have no idea how to debug this, if it is a backend or a reload bug.

RA/reload is known to have issues with word-mode paradoxical subregs on 
big-endian machines.  For example, on SPARC 64-bit, we run into similar 
problems for FP regs, which are 32-bit.  Likewise on HP-PA 64-bit I think.

So we have kludges in the back-end:

/* Defines invalid mode changes.  Borrowed from the PA port.

   SImode loads to floating-point registers are not zero-extended.
   The definition for LOAD_EXTEND_OP specifies that integer loads
   narrower than BITS_PER_WORD will be zero-extended.  As a result,
   we inhibit changes from SImode unless they are to a mode that is
   identical in size.

   Likewise for SFmode, since word-mode paradoxical subregs are
   problematic on big-endian architectures.  */

#define CANNOT_CHANGE_MODE_CLASS(FROM, TO, CLASS)		\
  (TARGET_ARCH64						\
   && GET_MODE_SIZE (FROM) == 4					\
   && GET_MODE_SIZE (TO) != 4					\
   ? reg_classes_intersect_p (CLASS, FP_REGS) : 0)

-- 
Eric Botcazou