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Re: combine two load insns
On 8 December 2010 17:37, Jeff Law <law@redhat.com> wrote:
> On 12/08/10 09:18, Frederic Riss wrote:
>>
>> OK, I see your point, but I tend to think the the odds of the register
>> allocator being able to coalesce the additional DI->SI moves in the
>> pre-IRA approach are by far higher that the odds of having merge
>> candidates after register allocation.
>
> I agree, but note that failure to coalesce leads to code quality regression.
Well, it really depends on the architecture. Moving between SImode
registers is usually nearly free, whereas accessing the memory is so
much more costly... If your architecture has a DI sized datapath to
memory, you actually divide the memory bandwidth requirement by 2 when
you pack SI loads together. This seems like a net win to me even if
you add 1 or 2 moves to the equation.
Fred