Re: Modelling of multiple condition code registers

[Ian Lance Taylor <iant at google dot com>]

Markus L <markusl.se78@gmail.com> writes:

> I have a question about modelling of condition codes in GCC. The
> target I am considering has the following characteristics:
>
> Associated with each register is a set of CC flags that are updated
> whenever that register is used as a destination of an operation that
> would normally update the CC register in a single CC machine. Example:
>
> add r0, r1, r2Â // updates r2's condition codes
> cmp r0, r1 // updates r1's condition codes
>
> Any instruction can be predicated on these condition codes, e.g.
>
> if (r2:ge) ld [r0], r1
> if(r1:ne) mpy r1, r2, r3
>
> So we have several CC registers and the one that will be updated for a
> given instruction directly depends on the destination register chosen
> for that instruction.
>
> My question is; would it be possible for GCC take advantage of these
> "extra" CC registers? And if that should be the case how would I go
> about modelling it?

I have not seen this before, and at first glance I don't see how to
really take advantage of it in gcc.  From your description, and the
existence of the cmp instruction, I assume that not every instruction
that sets the register sets the condition codes.  In that case, my first
thought would be that you should emit a cmp instruction before each
comparison, and then write a machine specific pass, perhaps in md_reorg,
which eliminates the unnecessary cmp instructions based on how the
values were stored in the register.  This pass could probably be
implemented using the LCM machinery.  An alternative would be to do the
reverse: write each conditional by testing the condition codes
associated with a register, and then walk the tree inserting cmp
instructions.  The general conditional execution you would do using
COND_EXEC as on other targets.

Ian