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Michael Kruse wrote:Although I mostly agree with this. I am not sure about universality of this claim. As an example, choosing x86 add insn instead of lea earlier could result in an additional spill and vise versa choosing lea could result in usage 3 different register and bigger code.
So, now my questions: How much do you think could this could improve
compiled code speed? Would the current GCC/YARA benefit from such an
optimization pass at all? What are the chances that this could get into
the main GCC tree if it shows up to be an improvement?
One of the major problems in gcc is the intertangling of instruction selection with register allocation and spill generation. If these could be separated it would almost certainly generate better code and be welcomed with open arms!
I'd prefer to implement this for the gcc, but my advisor wants me to do
it for the university's own compiler. Therefore I could also need
arguments why to do it for the GCC.
Because destroying reload(*) would be an incalculable public service and your name will be remembered in history as the one who slew the dragon? ;-)
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