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Re: Setting ARM PIC register (Was: RE: GCC 4.5.0 Status Report (2009-05-05))
Hi,
On Wed, 6 May 2009, Paolo Bonzini wrote:
> Looks like something like this could be useful to avoid code
> duplications in the backends:
>
> void
> emit_insn_at_top (rtx insn)
> {
> rtx scan;
>
> gcc_assert (current_ir_type () != IR_RTL_CFGLAYOUT);
> push_topmost_sequence ();
> scan = get_insns ();
> while (NEXT_INSN (scan) && !INSN_P (NEXT_INSN (scan)))
> scan = NEXT_INSN (scan);
>
> emit_insn_after (insn, scan);
> pop_topmost_sequence ();
> }
>
> mips16_gp_pseudo_reg () in config/mips/mips.c is already using something
> like that.
Or like alpha:
insert_insn_on_edge (seq, single_succ_edge (ENTRY_BLOCK_PTR));
That's not for the PIC load, but should work okay as expand from SSA
commits instructions on edges later. That actually seems even nicer IMO,
if it works...
Ciao,
Michael.