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Re: m32c: pointer math vs sizetype again
- From: DJ Delorie <dj at redhat dot com>
- To: "Richard Guenther" <richard dot guenther at gmail dot com>
- Cc: gcc at gcc dot gnu dot org
- Date: Wed, 1 Oct 2008 18:43:39 -0400
- Subject: Re: m32c: pointer math vs sizetype again
- References: <200809192352.m8JNq7Xs003011@greed.delorie.com> <200809302220.m8UMKIPj008507@greed.delorie.com> <84fc9c000810011511g56d55554oc1321be55bec411f@mail.gmail.com>
> I think this is the wrong place to fix this. If you would override
> the sizetypes precision from your target, would that fix it? That
> is, in stor-layout.c set_sizetype make the target allow adjusting
> the passed type (which is supposed to be sizetype). If at all then
> these types should be consistent.
The problem is that the chip has 24 bit pointers, but 16 bit
registers. It has math operations for 16 bit numbers and some 32 bit
numbers (the rest are emulated). It has a few operations for 24 bit
numbers. There are no C types for 24 bit numbers (PSImode is 32 bits
wide with 24 bit precision, if I tweak its precision manually it tries
to use bitfield instructions all over the place, if I don't it uses
"long int" which is wrong).
All I want for now is to treat ptr+int as a signed addition, not an
unsigned one. My patch is just trying to detect the case where a sign
extension is needed at all, and insert it.