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Re: insn does not satisfy its constraints
- From: Mohamed Shafi <shafitvm at yahoo dot com>
- To: Omar Torres <gcc dot omar at gmail dot com>
- Cc: gcc at gcc dot gnu dot org
- Date: Sun, 31 Aug 2008 22:52:02 -0700 (PDT)
- Subject: Re: insn does not satisfy its constraints
----- Original Message ----
> From: Omar Torres <gcc.omar@gmail.com>
> To: shafitvm@yahoo.com
> Cc: gcc@gcc.gnu.org
> Sent: Saturday, August 30, 2008 12:11:36 AM
> Subject: Re: insn does not satisfy its constraints
>
> shafi wrote:
> > Operand 0 is a register
> > Operand 1 is a memory
> > Operand 2 is a register
> >
> >
> >> The md description for this instruction is:
> >>
> >> ;; addhi3
> >> (define_expand "addhi3"
> >> [(set (match_operand:HI 0 "register_operand" "")
> >> (plus:HI (match_operand:HI 1 "cool_addhi_operand" "")
> >> (match_operand:HI 2 "cool_addhi_operand" "")))]
> >> ""
> >> "")
> >>
> >> (define_insn "*addhi3"
> >> [(set (match_operand:HI 0 "register_operand" "=r ,r ,r")
> >> (plus:HI (match_operand:HI 1 "cool_addhi_operand" "%0 ,rim,r")
> >> (match_operand:HI 2 "cool_addhi_operand" "rim,0 ,r")))]
> >> ""
> >>
> >
> > Do you have an option where operand 0 is reg and operand 1 is mem and
> > operand 2 is reg?
> >
> My purpose is to describe the three possible scenarios:
> 1) Operand 0 is a register
> Operand 1 is the same register as operand 0
> Operand 2 is a register, immediate or memory
>
> 2) Operand 0 is a register
> Operand 1 is a register, immediate or memory
> Operand 2 is the same register as operand 0
>
> 3) Operand 0 is a register
> Operand 2 is a register
> Operand 3 is also a register
>
>
> > I am not sure what rim is for?
> >
> rim = is a short cut for r, m, i. I think is is allow to mix several
> constrains like this, right?
>
So rim is a user define constraint. Then i think you may want to look properly into EXTRA_CONSTRAINT_STR. Probably this is where you might be going wrong.
HTH
Shafi