Re: -mfmovd enabled by default for SH2A but not for SH4

[Christian BRUEL <christian dot bruel at st dot com>]

Hello,

Looks like you are mixing ABIs. what is you fpscr setting ?

From my understanding, if the fpscr PR bit is set to 0 the 64-bit 
operation behaves as 2 32 bit operations (paired single precision). so I 
don't think you get an address error here.

The well defined behavior of the fmov instruction depends on the 
endianess and the SZ/PR bits setting in the fpscr register. My guess is 
that the default gcc value of 32 bits fmov instruction is the one that 
matches best all sh4 configurations (SZ/PR=1 is even undefined for some 
cores).
Changing its default would be possible if you change your ABI or have 
another multilib setting for startup files. But the current situation is 
that it is usually let to the user to explicitly provide their own fpscr 
setting when then want to change the fpmov size and aligns.

Cheers,

Christian


Naveen H.S. wrote:
> Hi,
>
>
> > > Have you got this error on the real SH2A-FPU hardware?
>
> Yes, we got this error on SH72513(SH2A) hardware. When the same code
> is run on simulator, the "address error" occurs on encountering the
> "fmov.d" instruction.
>
>
> > > couldn't find any description for 8-byte alignment restriction for
> > > double data on memory in my SH2A manual
>
> Please refer the section 3.3 "address errors" in the SH2A software 
> manual at the following link:-
> http://documentation.renesas.com/eng/products/mpumcu/rej09b0051_sh2a.pdf
> It is mentioned that "Double longword data accessed from other than 
> double longword boundary" results in address error.
>
> Regards,
> Naveen.H.S.
> KPIT Cummins Infosystems Ltd,
> Pune (INDIA) 
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