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Re: Redundant logical operations left after early splitting

Dave and Jeff,

Here are more details and I have include testcase, splitter patterns and RTL dump to show problem in more detail.

The testcase is:

unsigned long f (unsigned char  *P)
{
 unsigned long C;
 C  = ((unsigned long)P[1] << 24)
    | ((unsigned long)P[2] << 16)
    | ((unsigned long)P[3] <<  8)
    | ((unsigned long)P[4] <<  0);
 return C;
}

which normally produce horrible code with no significant impact of optimisation.

To solve this, back end patterns for zero_extend and the lshift by multiples of 8 were split into QImode moves.
The hope was that gcc would then collapse the QImode expression list such as 0|0|0|x or 0|0|y|0 into simple moves.
Here are splitter patterns (followed by more stuff):

;; xx<---x xx<---x xx<---x xx<---x xx<---x xx<---x xx<---x xx<---x xx<---x
;; zero extend
(define_insn_and_split "zero_extendqi<mode>2"
 [(set (match_operand:HIDI 0 "nonimmediate_operand" "")
       (zero_extend:HIDI (match_operand:QI 1 "nonimmediate_operand" "")))]
 ""
 "#"
 ""
 [(const_int 0)]
 "
     int i;
   enum machine_mode dmode = GET_MODE (operands[0]);
   int dsize = GET_MODE_SIZE (dmode);
   enum machine_mode smode = GET_MODE (operands[1]);
   int ssize = GET_MODE_SIZE (smode);
   rtx dword =  simplify_gen_subreg (smode, operands[0], dmode, 0);
   emit_move_insn (dword, operands[1]);
   for (i = ssize; i < dsize; i++)
   {
       rtx dbyte =  simplify_gen_subreg (QImode, operands[0], dmode, i);
       emit_move_insn (dbyte, const0_rtx);
   }
   DONE;
 ")

;byte shift is just a series of moves
;check src OR dest is in register, so the move will be ok

(define_insn_and_split "ashl<mode>3_const2p"
 [(set (match_operand:HIDI 0 "nonimmediate_operand"            "")

(ashift:HIDI (match_operand:HIDI 1 "register_operand" "")
(match_operand:HIDI 2 "const_int_operand" "i"))
)
]
"((INTVAL (operands[2]) % 8) == 0)
"
"#"
""
[(const_int 0)]
{
int i;
enum machine_mode mode;
mode = GET_MODE(operands[0]);
int size = GET_MODE_SIZE(mode);
HOST_WIDE_INT x = INTVAL (operands[2]); rtx dbytes[8], sbytes[8];
for (i = 0; i < size; i++)
{
dbytes[i] = simplify_gen_subreg (QImode, operands[0], mode, i);
sbytes[i] = simplify_gen_subreg (QImode, operands[1], mode, i);
}
int shift = x / 8;
if (shift > size) shift = size;
for (i = shift; i < size; i++)
{
emit_move_insn (dbytes[i], sbytes[i - shift]); }
for (i = 0; i < shift; i++)
{
emit_move_insn (dbytes[i], const0_rtx); }
}
)

;----------------------------------------------------------------

The result kinda works but we are left with OR x,0 (and some missed opportunities to propagate zero constant forward into OR)

The spliiters are matched up initially (zero_extend) or at combine - just as expected.

All the subregs appear as expected in split1. Naturally this produces a bunch of QI subregs many of which contain zero. No real change happens in RTL until local register allocation (lreg dump file). There are no redundant IOR Rm,0 in dump files before lreg pass. The only note is a reg dead on the pointer argument when it gets moved to a pointer register. (no reg equals or other dead notes until lreg pass)

In the lreg dump file I can see the propagation of many (but not all) constant 0 forward into the IOR instructions (eg Rn = 0, Rm= Rm | Rn => Rm = Rm|0). These remains in RTL and are output into final code. Loads of zero into registers which end up being unused are removed in latter passes.

I can remove IOR Rm,0 with a targetted splitter to create a NOP - which is my last resort.

So here is lreg dump extract:


;; Function f (f)

starting the processing of deferred insns
ending the processing of deferred insns
df_analyze called
df_worklist_dataflow_overeager:n_basic_blocks 3 n_edges 2 count 3 (    1)
df_worklist_dataflow_overeager:n_basic_blocks 3 n_edges 2 count 3 (    1)


Pass 0

Register 42 costs: POINTER_X_REGS:0 POINTER_Y_REGS:0 POINTER_Z_REGS:0 BASE_POINTER_REGS:0 POINTER_REGS:0 ADDW_REGS:8000 SIMPLE_LD_REGS:8000 LD_REGS:8000 NO_LD_REGS:8000 GENERAL_REGS:8000 ALL_REGS:10000 MEM:20000
Register 58 costs: POINTER_X_REGS:0 POINTER_Z_REGS:0 BASE_POINTER_REGS:0 POINTER_REGS:0 ADDW_REGS:0 SIMPLE_LD_REGS:0 LD_REGS:0 NO_LD_REGS:2000 GENERAL_REGS:2000 ALL_REGS:16000 MEM:16000
Register 59 costs: POINTER_X_REGS:0 POINTER_Z_REGS:0 BASE_POINTER_REGS:0 POINTER_REGS:0 ADDW_REGS:0 SIMPLE_LD_REGS:0 LD_REGS:0 NO_LD_REGS:2000 GENERAL_REGS:2000 ALL_REGS:16000 MEM:16000
Register 60 costs: POINTER_X_REGS:0 POINTER_Z_REGS:0 BASE_POINTER_REGS:0 POINTER_REGS:0 ADDW_REGS:0 SIMPLE_LD_REGS:0 LD_REGS:0 NO_LD_REGS:2000 GENERAL_REGS:2000 ALL_REGS:16000 MEM:16000
Register 61 costs: POINTER_X_REGS:0 POINTER_Z_REGS:0 BASE_POINTER_REGS:0 POINTER_REGS:0 ADDW_REGS:0 SIMPLE_LD_REGS:0 LD_REGS:0 NO_LD_REGS:0 GENERAL_REGS:0 ALL_REGS:16000 MEM:16000
Register 62 costs: POINTER_X_REGS:0 POINTER_Z_REGS:0 BASE_POINTER_REGS:0 POINTER_REGS:0 ADDW_REGS:0 SIMPLE_LD_REGS:0 LD_REGS:0 NO_LD_REGS:0 GENERAL_REGS:0 ALL_REGS:4000 MEM:4000
Register 63 costs: POINTER_X_REGS:0 POINTER_Z_REGS:0 BASE_POINTER_REGS:0 POINTER_REGS:0 ADDW_REGS:0 SIMPLE_LD_REGS:0 LD_REGS:0 NO_LD_REGS:2000 GENERAL_REGS:2000 ALL_REGS:2000 MEM:2000
Register 64 costs: POINTER_X_REGS:0 POINTER_Z_REGS:0 BASE_POINTER_REGS:0 POINTER_REGS:0 ADDW_REGS:0 SIMPLE_LD_REGS:0 LD_REGS:0 NO_LD_REGS:2000 GENERAL_REGS:2000 ALL_REGS:2000 MEM:2000
Register 65 costs: POINTER_X_REGS:0 POINTER_Z_REGS:0 BASE_POINTER_REGS:0 POINTER_REGS:0 ADDW_REGS:0 SIMPLE_LD_REGS:0 LD_REGS:0 NO_LD_REGS:2000 GENERAL_REGS:2000 ALL_REGS:2000 MEM:2000
Register 66 costs: POINTER_X_REGS:0 POINTER_Z_REGS:0 BASE_POINTER_REGS:0 POINTER_REGS:0 ADDW_REGS:0 SIMPLE_LD_REGS:0 LD_REGS:0 NO_LD_REGS:0 GENERAL_REGS:0 ALL_REGS:4000 MEM:4000
Register 67 costs: POINTER_X_REGS:0 POINTER_Z_REGS:0 BASE_POINTER_REGS:0 POINTER_REGS:0 ADDW_REGS:0 SIMPLE_LD_REGS:0 LD_REGS:0 NO_LD_REGS:2000 GENERAL_REGS:2000 ALL_REGS:4000 MEM:4000
Register 68 costs: POINTER_X_REGS:0 POINTER_Z_REGS:0 BASE_POINTER_REGS:0 POINTER_REGS:0 ADDW_REGS:0 SIMPLE_LD_REGS:0 LD_REGS:0 NO_LD_REGS:2000 GENERAL_REGS:2000 ALL_REGS:2000 MEM:2000
Register 69 costs: POINTER_X_REGS:0 POINTER_Z_REGS:0 BASE_POINTER_REGS:0 POINTER_REGS:0 ADDW_REGS:0 SIMPLE_LD_REGS:0 LD_REGS:0 NO_LD_REGS:2000 GENERAL_REGS:2000 ALL_REGS:2000 MEM:2000
Register 70 costs: POINTER_X_REGS:0 POINTER_Z_REGS:0 BASE_POINTER_REGS:0 POINTER_REGS:0 ADDW_REGS:0 SIMPLE_LD_REGS:0 LD_REGS:0 NO_LD_REGS:2000 GENERAL_REGS:2000 ALL_REGS:4000 MEM:4000
Register 71 costs: POINTER_X_REGS:0 POINTER_Z_REGS:0 BASE_POINTER_REGS:0 POINTER_REGS:0 ADDW_REGS:0 SIMPLE_LD_REGS:0 LD_REGS:0 NO_LD_REGS:2000 GENERAL_REGS:2000 ALL_REGS:4000 MEM:4000
Register 72 costs: POINTER_X_REGS:0 POINTER_Z_REGS:0 BASE_POINTER_REGS:0 POINTER_REGS:0 ADDW_REGS:0 SIMPLE_LD_REGS:0 LD_REGS:0 NO_LD_REGS:0 GENERAL_REGS:0 ALL_REGS:4000 MEM:4000
Register 73 costs: POINTER_X_REGS:0 POINTER_Z_REGS:0 BASE_POINTER_REGS:0 POINTER_REGS:0 ADDW_REGS:0 SIMPLE_LD_REGS:0 LD_REGS:0 NO_LD_REGS:0 GENERAL_REGS:0 ALL_REGS:4000 MEM:4000
Register 74 costs: POINTER_X_REGS:0 POINTER_Z_REGS:0 BASE_POINTER_REGS:0 POINTER_REGS:0 ADDW_REGS:0 SIMPLE_LD_REGS:0 LD_REGS:0 NO_LD_REGS:0 GENERAL_REGS:0 ALL_REGS:4000 MEM:4000
Register 75 costs: POINTER_X_REGS:0 POINTER_Z_REGS:0 BASE_POINTER_REGS:0 POINTER_REGS:0 ADDW_REGS:0 SIMPLE_LD_REGS:0 LD_REGS:0 NO_LD_REGS:2000 GENERAL_REGS:2000 ALL_REGS:4000 MEM:4000
Register 76 costs: POINTER_X_REGS:0 POINTER_Z_REGS:0 BASE_POINTER_REGS:0 POINTER_REGS:0 ADDW_REGS:0 SIMPLE_LD_REGS:0 LD_REGS:0 NO_LD_REGS:2000 GENERAL_REGS:2000 ALL_REGS:4000 MEM:4000
Register 77 costs: POINTER_X_REGS:0 POINTER_Z_REGS:0 BASE_POINTER_REGS:0 POINTER_REGS:0 ADDW_REGS:0 SIMPLE_LD_REGS:0 LD_REGS:0 NO_LD_REGS:2000 GENERAL_REGS:2000 ALL_REGS:4000 MEM:4000
Register 78 costs: POINTER_X_REGS:0 POINTER_Z_REGS:0 BASE_POINTER_REGS:0 POINTER_REGS:0 ADDW_REGS:0 SIMPLE_LD_REGS:0 LD_REGS:0 NO_LD_REGS:0 GENERAL_REGS:0 ALL_REGS:4000 MEM:4000
Register 79 costs: POINTER_X_REGS:0 POINTER_Z_REGS:0 BASE_POINTER_REGS:0 POINTER_REGS:0 ADDW_REGS:0 SIMPLE_LD_REGS:0 LD_REGS:0 NO_LD_REGS:2000 GENERAL_REGS:2000 ALL_REGS:4000 MEM:4000
Register 80 costs: POINTER_X_REGS:0 POINTER_Z_REGS:0 BASE_POINTER_REGS:0 POINTER_REGS:0 ADDW_REGS:0 SIMPLE_LD_REGS:0 LD_REGS:0 NO_LD_REGS:2000 GENERAL_REGS:2000 ALL_REGS:4000 MEM:4000
Register 81 costs: POINTER_X_REGS:0 POINTER_Z_REGS:0 BASE_POINTER_REGS:0 POINTER_REGS:0 ADDW_REGS:0 SIMPLE_LD_REGS:0 LD_REGS:0 NO_LD_REGS:2000 GENERAL_REGS:2000 ALL_REGS:2000 MEM:2000
Register 82 costs: POINTER_X_REGS:0 POINTER_Z_REGS:0 BASE_POINTER_REGS:0 POINTER_REGS:0 ADDW_REGS:0 SIMPLE_LD_REGS:0 LD_REGS:0 NO_LD_REGS:2000 GENERAL_REGS:2000 ALL_REGS:4000 MEM:4000
Register 83 costs: POINTER_X_REGS:0 POINTER_Z_REGS:0 BASE_POINTER_REGS:0 POINTER_REGS:0 ADDW_REGS:0 SIMPLE_LD_REGS:0 LD_REGS:0 NO_LD_REGS:0 GENERAL_REGS:0 ALL_REGS:4000 MEM:4000
Register 84 costs: POINTER_X_REGS:0 POINTER_Z_REGS:0 BASE_POINTER_REGS:0 POINTER_REGS:0 ADDW_REGS:0 SIMPLE_LD_REGS:0 LD_REGS:0 NO_LD_REGS:0 GENERAL_REGS:0 ALL_REGS:4000 MEM:4000
Register 85 costs: POINTER_X_REGS:0 POINTER_Z_REGS:0 BASE_POINTER_REGS:0 POINTER_REGS:0 ADDW_REGS:0 SIMPLE_LD_REGS:0 LD_REGS:0 NO_LD_REGS:0 GENERAL_REGS:0 ALL_REGS:4000 MEM:4000

 Register 42 pref POINTER_REGS
 Register 58 pref LD_REGS, else GENERAL_REGS
 Register 59 pref LD_REGS, else GENERAL_REGS
 Register 60 pref LD_REGS, else GENERAL_REGS
 Register 61 pref GENERAL_REGS or none
 Register 62 pref GENERAL_REGS or none
 Register 63 pref LD_REGS or none
 Register 64 pref LD_REGS or none
 Register 65 pref LD_REGS or none
 Register 66 pref GENERAL_REGS or none
 Register 67 pref LD_REGS, else GENERAL_REGS
 Register 68 pref LD_REGS or none
 Register 69 pref LD_REGS or none
 Register 70 pref LD_REGS, else GENERAL_REGS
 Register 71 pref LD_REGS, else GENERAL_REGS
 Register 72 pref GENERAL_REGS or none
 Register 73 pref GENERAL_REGS or none
 Register 74 pref GENERAL_REGS or none
 Register 75 pref LD_REGS, else GENERAL_REGS
 Register 76 pref LD_REGS, else GENERAL_REGS
 Register 77 pref LD_REGS, else GENERAL_REGS
 Register 78 pref GENERAL_REGS or none
 Register 79 pref LD_REGS, else GENERAL_REGS
 Register 80 pref LD_REGS, else GENERAL_REGS
 Register 81 pref LD_REGS or none
 Register 82 pref LD_REGS, else GENERAL_REGS
 Register 83 pref GENERAL_REGS or none
 Register 84 pref GENERAL_REGS or none
 Register 85 pref GENERAL_REGS or none


Pass 1

Register 42 costs: POINTER_X_REGS:0 POINTER_Y_REGS:0 POINTER_Z_REGS:0 BASE_POINTER_REGS:0 POINTER_REGS:0 ADDW_REGS:8000 SIMPLE_LD_REGS:8000 LD_REGS:8000 NO_LD_REGS:8000 GENERAL_REGS:8000 ALL_REGS:10000 MEM:20000
Register 58 costs: POINTER_X_REGS:0 POINTER_Z_REGS:0 BASE_POINTER_REGS:0 POINTER_REGS:0 ADDW_REGS:0 SIMPLE_LD_REGS:0 LD_REGS:0 NO_LD_REGS:2000 GENERAL_REGS:2000 ALL_REGS:16000 MEM:16000
Register 59 costs: POINTER_X_REGS:0 POINTER_Z_REGS:0 BASE_POINTER_REGS:0 POINTER_REGS:0 ADDW_REGS:0 SIMPLE_LD_REGS:0 LD_REGS:0 NO_LD_REGS:2000 GENERAL_REGS:2000 ALL_REGS:16000 MEM:16000
Register 60 costs: POINTER_X_REGS:0 POINTER_Z_REGS:0 BASE_POINTER_REGS:0 POINTER_REGS:0 ADDW_REGS:0 SIMPLE_LD_REGS:0 LD_REGS:0 NO_LD_REGS:2000 GENERAL_REGS:2000 ALL_REGS:16000 MEM:16000
Register 61 costs: POINTER_X_REGS:0 POINTER_Z_REGS:0 BASE_POINTER_REGS:0 POINTER_REGS:0 ADDW_REGS:0 SIMPLE_LD_REGS:0 LD_REGS:0 NO_LD_REGS:0 GENERAL_REGS:0 ALL_REGS:16000 MEM:16000
Register 62 costs: POINTER_X_REGS:0 POINTER_Z_REGS:0 BASE_POINTER_REGS:0 POINTER_REGS:0 ADDW_REGS:0 SIMPLE_LD_REGS:0 LD_REGS:0 NO_LD_REGS:0 GENERAL_REGS:0 ALL_REGS:4000 MEM:4000
Register 63 costs: POINTER_X_REGS:0 POINTER_Z_REGS:0 BASE_POINTER_REGS:0 POINTER_REGS:0 ADDW_REGS:0 SIMPLE_LD_REGS:0 LD_REGS:0 NO_LD_REGS:2000 GENERAL_REGS:2000 ALL_REGS:2000 MEM:2000
Register 64 costs: POINTER_X_REGS:0 POINTER_Z_REGS:0 BASE_POINTER_REGS:0 POINTER_REGS:0 ADDW_REGS:0 SIMPLE_LD_REGS:0 LD_REGS:0 NO_LD_REGS:2000 GENERAL_REGS:2000 ALL_REGS:2000 MEM:2000
Register 65 costs: POINTER_X_REGS:0 POINTER_Z_REGS:0 BASE_POINTER_REGS:0 POINTER_REGS:0 ADDW_REGS:0 SIMPLE_LD_REGS:0 LD_REGS:0 NO_LD_REGS:2000 GENERAL_REGS:2000 ALL_REGS:2000 MEM:2000
Register 66 costs: POINTER_X_REGS:0 POINTER_Z_REGS:0 BASE_POINTER_REGS:0 POINTER_REGS:0 ADDW_REGS:0 SIMPLE_LD_REGS:0 LD_REGS:0 NO_LD_REGS:0 GENERAL_REGS:0 ALL_REGS:4000 MEM:4000
Register 67 costs: POINTER_X_REGS:0 POINTER_Z_REGS:0 BASE_POINTER_REGS:0 POINTER_REGS:0 ADDW_REGS:0 SIMPLE_LD_REGS:0 LD_REGS:0 NO_LD_REGS:2000 GENERAL_REGS:2000 ALL_REGS:4000 MEM:4000
Register 68 costs: POINTER_X_REGS:0 POINTER_Z_REGS:0 BASE_POINTER_REGS:0 POINTER_REGS:0 ADDW_REGS:0 SIMPLE_LD_REGS:0 LD_REGS:0 NO_LD_REGS:2000 GENERAL_REGS:2000 ALL_REGS:2000 MEM:2000
Register 69 costs: POINTER_X_REGS:0 POINTER_Z_REGS:0 BASE_POINTER_REGS:0 POINTER_REGS:0 ADDW_REGS:0 SIMPLE_LD_REGS:0 LD_REGS:0 NO_LD_REGS:2000 GENERAL_REGS:2000 ALL_REGS:2000 MEM:2000
Register 70 costs: POINTER_X_REGS:0 POINTER_Z_REGS:0 BASE_POINTER_REGS:0 POINTER_REGS:0 ADDW_REGS:0 SIMPLE_LD_REGS:0 LD_REGS:0 NO_LD_REGS:2000 GENERAL_REGS:2000 ALL_REGS:4000 MEM:4000
Register 71 costs: POINTER_X_REGS:0 POINTER_Z_REGS:0 BASE_POINTER_REGS:0 POINTER_REGS:0 ADDW_REGS:0 SIMPLE_LD_REGS:0 LD_REGS:0 NO_LD_REGS:2000 GENERAL_REGS:2000 ALL_REGS:4000 MEM:4000
Register 72 costs: POINTER_X_REGS:0 POINTER_Z_REGS:0 BASE_POINTER_REGS:0 POINTER_REGS:0 ADDW_REGS:0 SIMPLE_LD_REGS:0 LD_REGS:0 NO_LD_REGS:0 GENERAL_REGS:0 ALL_REGS:4000 MEM:4000
Register 73 costs: POINTER_X_REGS:0 POINTER_Z_REGS:0 BASE_POINTER_REGS:0 POINTER_REGS:0 ADDW_REGS:0 SIMPLE_LD_REGS:0 LD_REGS:0 NO_LD_REGS:0 GENERAL_REGS:0 ALL_REGS:4000 MEM:4000
Register 74 costs: POINTER_X_REGS:0 POINTER_Z_REGS:0 BASE_POINTER_REGS:0 POINTER_REGS:0 ADDW_REGS:0 SIMPLE_LD_REGS:0 LD_REGS:0 NO_LD_REGS:0 GENERAL_REGS:0 ALL_REGS:4000 MEM:4000
Register 75 costs: POINTER_X_REGS:0 POINTER_Z_REGS:0 BASE_POINTER_REGS:0 POINTER_REGS:0 ADDW_REGS:0 SIMPLE_LD_REGS:0 LD_REGS:0 NO_LD_REGS:2000 GENERAL_REGS:2000 ALL_REGS:4000 MEM:4000
Register 76 costs: POINTER_X_REGS:0 POINTER_Z_REGS:0 BASE_POINTER_REGS:0 POINTER_REGS:0 ADDW_REGS:0 SIMPLE_LD_REGS:0 LD_REGS:0 NO_LD_REGS:2000 GENERAL_REGS:2000 ALL_REGS:4000 MEM:4000
Register 77 costs: POINTER_X_REGS:0 POINTER_Z_REGS:0 BASE_POINTER_REGS:0 POINTER_REGS:0 ADDW_REGS:0 SIMPLE_LD_REGS:0 LD_REGS:0 NO_LD_REGS:2000 GENERAL_REGS:2000 ALL_REGS:4000 MEM:4000
Register 78 costs: POINTER_X_REGS:0 POINTER_Z_REGS:0 BASE_POINTER_REGS:0 POINTER_REGS:0 ADDW_REGS:0 SIMPLE_LD_REGS:0 LD_REGS:0 NO_LD_REGS:0 GENERAL_REGS:0 ALL_REGS:4000 MEM:4000
Register 79 costs: POINTER_X_REGS:0 POINTER_Z_REGS:0 BASE_POINTER_REGS:0 POINTER_REGS:0 ADDW_REGS:0 SIMPLE_LD_REGS:0 LD_REGS:0 NO_LD_REGS:2000 GENERAL_REGS:2000 ALL_REGS:4000 MEM:4000
Register 80 costs: POINTER_X_REGS:0 POINTER_Z_REGS:0 BASE_POINTER_REGS:0 POINTER_REGS:0 ADDW_REGS:0 SIMPLE_LD_REGS:0 LD_REGS:0 NO_LD_REGS:2000 GENERAL_REGS:2000 ALL_REGS:4000 MEM:4000
Register 81 costs: POINTER_X_REGS:0 POINTER_Z_REGS:0 BASE_POINTER_REGS:0 POINTER_REGS:0 ADDW_REGS:0 SIMPLE_LD_REGS:0 LD_REGS:0 NO_LD_REGS:2000 GENERAL_REGS:2000 ALL_REGS:2000 MEM:2000
Register 82 costs: POINTER_X_REGS:0 POINTER_Z_REGS:0 BASE_POINTER_REGS:0 POINTER_REGS:0 ADDW_REGS:0 SIMPLE_LD_REGS:0 LD_REGS:0 NO_LD_REGS:2000 GENERAL_REGS:2000 ALL_REGS:4000 MEM:4000
Register 83 costs: POINTER_X_REGS:0 POINTER_Z_REGS:0 BASE_POINTER_REGS:0 POINTER_REGS:0 ADDW_REGS:0 SIMPLE_LD_REGS:0 LD_REGS:0 NO_LD_REGS:0 GENERAL_REGS:0 ALL_REGS:4000 MEM:4000
Register 84 costs: POINTER_X_REGS:0 POINTER_Z_REGS:0 BASE_POINTER_REGS:0 POINTER_REGS:0 ADDW_REGS:0 SIMPLE_LD_REGS:0 LD_REGS:0 NO_LD_REGS:0 GENERAL_REGS:0 ALL_REGS:4000 MEM:4000
Register 85 costs: POINTER_X_REGS:0 POINTER_Z_REGS:0 BASE_POINTER_REGS:0 POINTER_REGS:0 ADDW_REGS:0 SIMPLE_LD_REGS:0 LD_REGS:0 NO_LD_REGS:0 GENERAL_REGS:0 ALL_REGS:4000 MEM:4000

rescanning insn with uid = 78.
deleting insn with uid = 78.
deleting insn with uid = 76.
rescanning insn with uid = 75.
deleting insn with uid = 75.
deleting insn with uid = 71.
rescanning insn with uid = 74.
deleting insn with uid = 74.
deleting insn with uid = 70.
rescanning insn with uid = 68.
deleting insn with uid = 68.
deleting insn with uid = 64.
rescanning insn with uid = 67.
deleting insn with uid = 67.
deleting insn with uid = 63.
rescanning insn with uid = 66.
deleting insn with uid = 66.
deleting insn with uid = 62.
rescanning insn with uid = 58.
deleting insn with uid = 58.
deleting insn with uid = 55.
rescanning insn with uid = 57.
deleting insn with uid = 57.
deleting insn with uid = 54.
rescanning insn with uid = 53.
deleting insn with uid = 53.
deleting insn with uid = 49.
86 registers.

Register 36 used 0 times across 0 insns; set 0 times; dies in 0 places; 2 bytes; NO_REGS or none; pointer.

Register 37 used 0 times across 0 insns; set 0 times; dies in 0 places; 2 bytes; NO_REGS or none; pointer.

Register 38 used 0 times across 0 insns; set 0 times; dies in 0 places; 2 bytes; NO_REGS or none; pointer.

Register 39 used 0 times across 0 insns; set 0 times; dies in 0 places; 2 bytes; NO_REGS or none; pointer.

Register 40 used 0 times across 0 insns; set 0 times; dies in 0 places; 2 bytes; NO_REGS or none; pointer.

Register 41 used 0 times across 0 insns; set 0 times; dies in 0 places; NO_REGS or none.

Register 42 used 5 times across 32 insns in block 2; set 1 time; user var; 2 bytes; pref POINTER_REGS; pointer.

Register 43 used 0 times across 0 insns; set 0 times; dies in 0 places; NO_REGS or none.

Register 44 used 0 times across 0 insns; set 0 times; dies in 0 places; NO_REGS or none.

Register 45 used 0 times across 0 insns; set 0 times; dies in 0 places; 4 bytes; NO_REGS or none.

Register 46 used 0 times across 0 insns; set 0 times; dies in 0 places; NO_REGS or none.

Register 47 used 0 times across 0 insns; set 0 times; dies in 0 places; NO_REGS or none.

Register 48 used 0 times across 0 insns; set 0 times; dies in 0 places; 4 bytes; NO_REGS or none.

Register 49 used 0 times across 0 insns; set 0 times; dies in 0 places; NO_REGS or none.

Register 50 used 0 times across 0 insns; set 0 times; dies in 0 places; 4 bytes; NO_REGS or none.

Register 51 used 0 times across 0 insns; set 0 times; dies in 0 places; NO_REGS or none.

Register 52 used 0 times across 0 insns; set 0 times; dies in 0 places; NO_REGS or none.

Register 53 used 0 times across 0 insns; set 0 times; dies in 0 places; NO_REGS or none.

Register 54 used 0 times across 0 insns; set 0 times; dies in 0 places; NO_REGS or none.

Register 55 used 0 times across 0 insns; set 0 times; dies in 0 places; NO_REGS or none.

Register 56 used 0 times across 0 insns; set 0 times; dies in 0 places; NO_REGS or none.

Register 57 used 0 times across 0 insns; set 0 times; dies in 0 places; 4 bytes; NO_REGS or none.

Register 58 used 8 times across 42 insns in block 2; set 4 times; pref LD_REGS, else GENERAL_REGS.

Register 59 used 8 times across 42 insns in block 2; set 4 times; pref LD_REGS, else GENERAL_REGS.

Register 60 used 8 times across 42 insns in block 2; set 4 times; pref LD_REGS, else GENERAL_REGS.

Register 61 used 8 times across 46 insns in block 2; set 4 times; GENERAL_REGS or none.

Register 62 used 2 times across 5 insns in block 2; set 1 time; GENERAL_REGS or none.

Register 63 used 1 times across 2 insns in block 2; set 1 time; dies in 0 places; LD_REGS or none.

Register 64 used 1 times across 2 insns in block 2; set 1 time; dies in 0 places; LD_REGS or none.

Register 65 used 1 times across 2 insns in block 2; set 1 time; dies in 0 places; LD_REGS or none.

Register 66 used 2 times across 5 insns in block 2; set 1 time; GENERAL_REGS or none.

Register 67 used 0 times across 10 insns in block 2; set 1 time; pref LD_REGS, else GENERAL_REGS.

Register 68 used 1 times across 2 insns in block 2; set 1 time; dies in 0 places; LD_REGS or none.

Register 69 used 1 times across 2 insns in block 2; set 1 time; dies in 0 places; LD_REGS or none.

Register 70 used 0 times across 8 insns in block 2; set 1 time; pref LD_REGS, else GENERAL_REGS.

Register 71 used 0 times across 8 insns in block 2; set 1 time; pref LD_REGS, else GENERAL_REGS.

Register 72 used 2 times across 8 insns in block 2; set 1 time; GENERAL_REGS or none.

Register 73 used 2 times across 8 insns in block 2; set 1 time; GENERAL_REGS or none.

Register 74 used 2 times across 5 insns in block 2; set 1 time; GENERAL_REGS or none.

Register 75 used 0 times across 10 insns in block 2; set 1 time; pref LD_REGS, else GENERAL_REGS.

Register 76 used 0 times across 10 insns in block 2; set 1 time; pref LD_REGS, else GENERAL_REGS.

Register 77 used 0 times across 10 insns in block 2; set 1 time; pref LD_REGS, else GENERAL_REGS.

Register 78 used 2 times across 5 insns in block 2; set 1 time; GENERAL_REGS or none.

Register 79 used 0 times across 10 insns in block 2; set 1 time; pref LD_REGS, else GENERAL_REGS.

Register 80 used 0 times across 10 insns in block 2; set 1 time; pref LD_REGS, else GENERAL_REGS.

Register 81 used 1 times across 2 insns in block 2; set 1 time; dies in 0 places; LD_REGS or none.

Register 82 used 0 times across 6 insns in block 2; set 1 time; pref LD_REGS, else GENERAL_REGS.

Register 83 used 2 times across 7 insns in block 2; set 1 time; GENERAL_REGS or none.

Register 84 used 2 times across 7 insns in block 2; set 1 time; GENERAL_REGS or none.

Register 85 used 2 times across 7 insns in block 2; set 1 time; GENERAL_REGS or none.

3 basic blocks, 2 edges.

Basic block 0 , next 2, loop_depth 0, count 0, freq 10000, maybe hot.
Predecessors:
;; bb 0 artificial_defs: { d0(2){ }d1(8){ }d2(9){ }d3(10){ }d4(11){ }d5(12){ }d6(13){ }d7(14){ }d8(15){ }d9(16){ }d10(17){ }d11(18){ }d12(19){ }d13(20){ }d14(21){ }d16(22){ }d18(23){ }d20(24){ }d22(25){ }d23(28){ }d24(32){ }d25(34){ }}
;; bb 0 artificial_uses: { }
;; lr in ;; lr use ;; lr def 2 [r2] 8 [r8] 9 [r9] 10 [r10] 11 [r11] 12 [r12] 13 [r13] 14 [r14] 15 [r15] 16 [r16] 17 [r17] 18 [r18] 19 [r19] 20 [r20] 21 [r21] 22 [r22] 23 [r23] 24 [r24] 25 [r25] 28 [r28] 32 [__SP_L__] 34 [argL]
;; live in ;; live gen 2 [r2] 8 [r8] 9 [r9] 10 [r10] 11 [r11] 12 [r12] 13 [r13] 14 [r14] 15 [r15] 16 [r16] 17 [r17] 18 [r18] 19 [r19] 20 [r20] 21 [r21] 22 [r22] 23 [r23] 24 [r24] 25 [r25] 28 [r28] 32 [__SP_L__] 34 [argL]
;; live kill 

Successors:  2 [100.0%]  (fallthru)
;; lr  out      24 [r24] 25 [r25] 28 [r28] 32 [__SP_L__] 34 [argL]
;; live  out      24 [r24] 25 [r25] 28 [r28] 32 [__SP_L__] 34 [argL]


Basic block 2 , prev 0, next 1, loop_depth 0, count 0, freq 10000, maybe hot.
Predecessors: ENTRY [100.0%] (fallthru)
;; bb 2 artificial_defs: { }
;; bb 2 artificial_uses: { u0(28){ }u1(32){ }u2(34){ }}
;; lr in 24 [r24] 25 [r25] 28 [r28] 32 [__SP_L__] 34 [argL]
;; lr use 24 [r24] 25 [r25] 28 [r28] 32 [__SP_L__] 34 [argL]
;; lr def 22 [r22] 23 [r23] 24 [r24] 25 [r25] 42 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85
;; live in 24 [r24] 25 [r25] 28 [r28] 32 [__SP_L__] 34 [argL]
;; live gen 22 [r22] 23 [r23] 24 [r24] 25 [r25] 42 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85
;; live kill

Successors: EXIT [100.0%] (fallthru)
;; lr out 22 [r22] 23 [r23] 24 [r24] 25 [r25] 28 [r28] 32 [__SP_L__] 34 [argL]
;; live out 22 [r22] 23 [r23] 24 [r24] 25 [r25] 28 [r28] 32 [__SP_L__] 34 [argL]


Basic block 1 , prev 2, loop_depth 0, count 0, freq 10000, maybe hot.
Predecessors: 2 [100.0%] (fallthru)
;; bb 1 artificial_defs: { }
;; bb 1 artificial_uses: { u26(22){ }u27(23){ }u28(24){ }u29(25){ }u30(28){ }u31(32){ }}
;; lr in 22 [r22] 23 [r23] 24 [r24] 25 [r25] 28 [r28] 32 [__SP_L__]
;; lr use 22 [r22] 23 [r23] 24 [r24] 25 [r25] 28 [r28] 32 [__SP_L__]
;; lr def ;; live in 22 [r22] 23 [r23] 24 [r24] 25 [r25] 28 [r28] 32 [__SP_L__]
;; live gen ;; live kill

Successors:
;; lr out ;; live out 


;; Register 42 in 30.
;; Register 58 in 22.
;; Register 59 in 23.
;; Register 60 in 24.
;; Register 61 in 25.
;; Register 62 in 25.
;; Register 66 in 18.
;; Register 72 in 18.
;; Register 73 in 19.
;; Register 74 in 18.
;; Register 78 in 18.
;; Register 83 in 18.
;; Register 84 in 19.
;; Register 85 in 20.


f

Dataflow summary:
;; invalidated by call 0 [r0] 1 [r1] 18 [r18] 19 [r19] 20 [r20] 21 [r21] 22 [r22] 23 [r23] 24 [r24] 25 [r25] 26 [r26] 27 [r27] 30 [r30] 31 [r31] 33 [__SP_H__] 35 [argH]
;; hardware regs used 28 [r28] 32 [__SP_L__] 34 [argL]
;; regular block artificial uses 28 [r28] 32 [__SP_L__] 34 [argL]
;; eh block artificial uses 28 [r28] 32 [__SP_L__] 34 [argL]
;; entry block defs 2 [r2] 8 [r8] 9 [r9] 10 [r10] 11 [r11] 12 [r12] 13 [r13] 14 [r14] 15 [r15] 16 [r16] 17 [r17] 18 [r18] 19 [r19] 20 [r20] 21 [r21] 22 [r22] 23 [r23] 24 [r24] 25 [r25] 28 [r28] 32 [__SP_L__] 34 [argL]
;; exit block uses 22 [r22] 23 [r23] 24 [r24] 25 [r25] 28 [r28] 32 [__SP_L__]
;; regs ever live 22[r22] 23[r23] 24[r24] 25[r25]
(note 1 0 4 NOTE_INSN_DELETED)

;; Start of basic block ( 0) -> 2
;; bb 2 artificial_defs: { }
;; bb 2 artificial_uses: { u0(28){ }u1(32){ }u2(34){ }}
;; lr in 24 [r24] 25 [r25] 28 [r28] 32 [__SP_L__] 34 [argL]
;; lr use 24 [r24] 25 [r25] 28 [r28] 32 [__SP_L__] 34 [argL]
;; lr def 22 [r22] 23 [r23] 24 [r24] 25 [r25] 42 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85
;; live in 24 [r24] 25 [r25] 28 [r28] 32 [__SP_L__] 34 [argL]
;; live gen 22 [r22] 23 [r23] 24 [r24] 25 [r25] 42 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85
;; live kill 

;; Pred edge  ENTRY [100.0%]  (fallthru)
(note 4 1 2 2 [bb 2] NOTE_INSN_BASIC_BLOCK)

(insn 2 4 3 2 tests.c:10 (set (reg/v/f:HI 42 [ P ])
(reg:HI 24 r24 [ P ])) 8 {*movhi} (expr_list:REG_DEAD (reg:HI 24 r24 [ P ])
(nil)))

(note 3 2 39 2 NOTE_INSN_FUNCTION_BEG)

(insn 39 3 40 2 tests.c:10 (set (reg:QI 62)
       (mem:QI (plus:HI (reg/v/f:HI 42 [ P ])
               (const_int 1 [0x1])) [0 S1 A8])) 4 {*movqi} (nil))

(insn 40 39 41 2 tests.c:10 (set (reg:QI 63 [+1 ])
(const_int 0 [0x0])) 4 {*movqi} (expr_list:REG_EQUIV (const_int 0 [0x0])
(expr_list:REG_UNUSED (reg:QI 63 [+1 ])
(nil))))

(insn 41 40 42 2 tests.c:10 (set (reg:QI 64 [+2 ])
(const_int 0 [0x0])) 4 {*movqi} (expr_list:REG_EQUIV (const_int 0 [0x0])
(expr_list:REG_UNUSED (reg:QI 64 [+2 ])
(nil))))

(insn 42 41 43 2 tests.c:10 (set (reg:QI 65 [+3 ])
(const_int 0 [0x0])) 4 {*movqi} (expr_list:REG_EQUIV (const_int 0 [0x0])
(expr_list:REG_UNUSED (reg:QI 65 [+3 ])
(nil))))

(insn 43 42 44 2 tests.c:10 (set (reg:QI 61 [+3 ])
       (reg:QI 62)) 4 {*movqi} (expr_list:REG_DEAD (reg:QI 62)
       (nil)))

(insn 44 43 45 2 tests.c:10 (set (reg:QI 58)
(const_int 0 [0x0])) 4 {*movqi} (expr_list:REG_EQUAL (const_int 0 [0x0])
(nil)))

(insn 45 44 46 2 tests.c:10 (set (reg:QI 59 [+1 ])
(const_int 0 [0x0])) 4 {*movqi} (expr_list:REG_EQUAL (const_int 0 [0x0])
(nil)))

(insn 46 45 47 2 tests.c:10 (set (reg:QI 60 [+2 ])
(const_int 0 [0x0])) 4 {*movqi} (expr_list:REG_EQUAL (const_int 0 [0x0])
(nil)))

(insn 47 46 48 2 tests.c:10 (const_int 0 [0x0]) 110 {nop} (nil))

(insn 48 47 50 2 tests.c:10 (set (reg:QI 66)
       (mem:QI (plus:HI (reg/v/f:HI 42 [ P ])
               (const_int 2 [0x2])) [0 S1 A8])) 4 {*movqi} (nil))

(insn 50 48 51 2 tests.c:10 (set (reg:QI 68 [+2 ])
(const_int 0 [0x0])) 4 {*movqi} (expr_list:REG_EQUIV (const_int 0 [0x0])
(expr_list:REG_UNUSED (reg:QI 68 [+2 ])
(nil))))

(insn 51 50 52 2 tests.c:10 (set (reg:QI 69 [+3 ])
(const_int 0 [0x0])) 4 {*movqi} (expr_list:REG_EQUIV (const_int 0 [0x0])
(expr_list:REG_UNUSED (reg:QI 69 [+3 ])
(nil))))

(insn 52 51 53 2 tests.c:10 (set (reg:QI 72 [+2 ])
       (reg:QI 66)) 4 {*movqi} (expr_list:REG_DEAD (reg:QI 66)
       (nil)))

(insn 53 52 56 2 tests.c:10 (set (reg:QI 73 [+3 ])
       (const_int 0 [0x0])) 4 {*movqi} (nil))

(insn 56 53 57 2 tests.c:10 (const_int 0 [0x0]) 110 {nop} (nil))

(insn 57 56 58 2 tests.c:10 (set (reg:QI 58)
       (ior:QI (reg:QI 58)
           (const_int 0 [0x0]))) 63 {iorqi3} (nil))

(insn 58 57 59 2 tests.c:10 (set (reg:QI 59 [+1 ])
       (ior:QI (reg:QI 59 [+1 ])
           (const_int 0 [0x0]))) 63 {iorqi3} (nil))

(insn 59 58 60 2 tests.c:10 (set (reg:QI 60 [+2 ])
(ior:QI (reg:QI 60 [+2 ])
(reg:QI 72 [+2 ]))) 63 {iorqi3} (expr_list:REG_DEAD (reg:QI 72 [+2 ])
(nil)))

(insn 60 59 61 2 tests.c:10 (set (reg:QI 61 [+3 ])
(ior:QI (reg:QI 61 [+3 ])
(reg:QI 73 [+3 ]))) 63 {iorqi3} (expr_list:REG_DEAD (reg:QI 73 [+3 ])
(nil)))

(insn 61 60 65 2 tests.c:10 (set (reg:QI 74)
       (mem:QI (plus:HI (reg/v/f:HI 42 [ P ])
               (const_int 4 [0x4])) [0 S1 A8])) 4 {*movqi} (nil))

(insn 65 61 66 2 tests.c:10 (set (reg:QI 58)
       (ior:QI (reg:QI 58)
           (reg:QI 74))) 63 {iorqi3} (expr_list:REG_DEAD (reg:QI 74)
       (nil)))

(insn 66 65 67 2 tests.c:10 (set (reg:QI 59 [+1 ])
       (ior:QI (reg:QI 59 [+1 ])
           (const_int 0 [0x0]))) 63 {iorqi3} (nil))

(insn 67 66 68 2 tests.c:10 (set (reg:QI 60 [+2 ])
       (ior:QI (reg:QI 60 [+2 ])
           (const_int 0 [0x0]))) 63 {iorqi3} (nil))

(insn 68 67 69 2 tests.c:10 (set (reg:QI 61 [+3 ])
       (ior:QI (reg:QI 61 [+3 ])
           (const_int 0 [0x0]))) 63 {iorqi3} (nil))

(insn 69 68 72 2 tests.c:10 (set (reg:QI 78)
(mem:QI (plus:HI (reg/v/f:HI 42 [ P ])
(const_int 3 [0x3])) [0 S1 A8])) 4 {*movqi} (expr_list:REG_DEAD (reg/v/f:HI 42 [ P ])
(nil)))

(insn 72 69 73 2 tests.c:10 (set (reg:QI 81 [+3 ])
(const_int 0 [0x0])) 4 {*movqi} (expr_list:REG_EQUIV (const_int 0 [0x0])
(expr_list:REG_UNUSED (reg:QI 81 [+3 ])
(nil))))

(insn 73 72 74 2 tests.c:10 (set (reg:QI 83 [+1 ])
       (reg:QI 78)) 4 {*movqi} (expr_list:REG_DEAD (reg:QI 78)
       (nil)))

(insn 74 73 75 2 tests.c:10 (set (reg:QI 84 [+2 ])
       (const_int 0 [0x0])) 4 {*movqi} (nil))

(insn 75 74 77 2 tests.c:10 (set (reg:QI 85 [+3 ])
       (const_int 0 [0x0])) 4 {*movqi} (nil))

(insn 77 75 78 2 tests.c:10 (const_int 0 [0x0]) 110 {nop} (nil))

(insn 78 77 79 2 tests.c:10 (set (reg:QI 58)
       (ior:QI (reg:QI 58)
           (const_int 0 [0x0]))) 63 {iorqi3} (nil))

(insn 79 78 80 2 tests.c:10 (set (reg:QI 59 [+1 ])
(ior:QI (reg:QI 59 [+1 ])
(reg:QI 83 [+1 ]))) 63 {iorqi3} (expr_list:REG_DEAD (reg:QI 83 [+1 ])
(nil)))

(insn 80 79 81 2 tests.c:10 (set (reg:QI 60 [+2 ])
(ior:QI (reg:QI 60 [+2 ])
(reg:QI 84 [+2 ]))) 63 {iorqi3} (expr_list:REG_DEAD (reg:QI 84 [+2 ])
(nil)))

(insn 81 80 35 2 tests.c:10 (set (reg:QI 61 [+3 ])
(ior:QI (reg:QI 61 [+3 ])
(reg:QI 85 [+3 ]))) 63 {iorqi3} (expr_list:REG_DEAD (reg:QI 85 [+3 ])
(nil)))

(insn 35 81 36 2 tests.c:17 (set (reg:QI 22 r22 [ <result> ])
       (reg:QI 58)) 4 {*movqi} (expr_list:REG_DEAD (reg:QI 58)
       (nil)))

(insn 36 35 37 2 tests.c:17 (set (reg:QI 23 r23 [+1 ])
       (reg:QI 59 [+1 ])) 4 {*movqi} (expr_list:REG_DEAD (reg:QI 59 [+1 ])
       (nil)))

(insn 37 36 38 2 tests.c:17 (set (reg:QI 24 r24 [+2 ])
       (reg:QI 60 [+2 ])) 4 {*movqi} (expr_list:REG_DEAD (reg:QI 60 [+2 ])
       (nil)))

(insn 38 37 26 2 tests.c:17 (set (reg:QI 25 r25 [+3 ])
       (reg:QI 61 [+3 ])) 4 {*movqi} (expr_list:REG_DEAD (reg:QI 61 [+3 ])
       (nil)))

(insn 26 38 0 2 tests.c:17 (use (reg/i:SI 22 r22)) -1 (nil))
;; End of basic block 2 -> ( 1)
;; lr out 22 [r22] 23 [r23] 24 [r24] 25 [r25] 28 [r28] 32 [__SP_L__] 34 [argL]
;; live out 22 [r22] 23 [r23] 24 [r24] 25 [r25] 28 [r28] 32 [__SP_L__] 34 [argL]


;; Succ edge EXIT [100.0%] (fallthru)



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