Register Numbers during machine dependent reorg?

["Balaji V. Iyer" <bviyer at ncsu dot edu>]

Hello Everyone,
   I am currently working with MIPS port of gcc-4.0.2 by using segmented
register files (like a multi-core approach). This is what i would like
to do:

I would like to assign instructions whose destination registers are
between 0 to 7 to core 1, 8-15 to core 2 and so forth.


I would like some advice about doing this efficiently in GCC? Can I do
this in machine dependent reorganization phase? When the compiler reaches
this phase, does it know the register numbers already?

I am OK with modifying the main-stream GCC files, the whole change doesn't
have to be in the files of config/mips directory.

Any help is highly appreciated.

Thanking You,

Yours Sincerely,

Balaji V. Iyer.

PS. Please CC me in your response since I am not a subscriber of this
mailing list.


====================================================
Balaji V. Iyer
PhD Student,
Center for Efficient, Secure and Reliable Computing
Department of Electrical and Computer Engineering
North Carolina State University.
====================================================