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Re: REG_ALLOC_ORDER and Altivec registers
- From: Tehila Meyzels <TEHILA at il dot ibm dot com>
- To: Revital1 Eres <ERES at il dot ibm dot com>
- Cc: gcc at gcc dot gnu dot org
- Date: Thu, 1 Mar 2007 10:57:04 +0200
- Subject: Re: REG_ALLOC_ORDER and Altivec registers
Revital Eres wrote on 01/03/2007 10:37:36:
>
> Hello,
>
> I wonder why this order (non-consecutive, decreasing) of Altivec
registers
> was chosen when specifying the allocation order in REG_ALLOC_ORDER.
>
> (taken from rs6000.h)
>
> /* AltiVec registers. */ \
> 77, 78, \
> 90, 89, 88, 87, 86, 85, 84, 83, 82, 81, 80, \
> 79, \
> 96, 95, 94, 93, 92, 91, \
> 108, 107, 106, 105, 104, 103, 102, 101, 100, 99, 98, 97, \
> 109, 110, \
> 111, 112, 113 \
>
I think part of the answer can be found here:
http://gcc.gnu.org/ml/gcc/2003-06/msg00902.html
"We have found that re-arranging the REG_ALLOC_ORDER in rs6000.h so that
all
the FP registers come after the integer registers greatly reduces the
tendency of the compiler to generate code that moves 8-byte quantites
through
the FP registers."
Tehila.
> Thanks,
> Revital
>