This is the mail archive of the
gcc@gcc.gnu.org
mailing list for the GCC project.
Re: Abt long long support
On 11/10/06, Mike Stump <mrs@apple.com> wrote:
On Nov 9, 2006, at 6:39 AM, Mohamed Shafi wrote:
> When i diff the rtl dumps for programs passing negative value with and
> without frame pointer i find changes from file.greg .
A quick glance at the rtl shows that insn 95 tries to use [a4+4] but
insn 94 clobbered a4 already, also d3 is used by insn 93, but there
isn't a set for it.
The following part of the rtl dump of greg pass is the one which is
giving the wrong output.
(insn 90 29 91 6 (set (reg:SI 12 a4)
(const_int -16 [0xfffffff0])) 17 {movsi_short_const} (nil)
(nil))
(insn 91 90 94 6 (parallel [
(set (reg:SI 12 a4)
(plus:SI (reg:SI 12 a4)
(reg/f:SI 14 a6)))
(clobber (reg:CC 21 cc))
]) 29 {addsi3} (nil)
(expr_list:REG_EQUIV (plus:SI (reg/f:SI 14 a6)
(const_int -16 [0xfffffff0]))
(nil)))
(insn 94 91 95 6 (set (reg:SI 12 a4)
(mem/c:SI (reg:SI 12 a4) [0 D.1863+0 S4 A32])) 15 {movsi_load} (nil)
(nil))
(insn 95 94 31 6 (set (reg:SI 13 a5 [orig:12+4 ] [12])
(mem/c:SI (plus:SI (reg:SI 12 a4)
(const_int 4 [0x4])) [0 D.1863+4 S4 A32])) 15 {movsi_load} (nil)
(nil))
(insn 31 95 87 6 (parallel [
(set (reg:DI 2 d2)
(minus:DI (reg:DI 0 d0 [34])
(reg:DI 12 a4)))
(clobber (reg:CC 21 cc))
]) 33 {subdi3} (nil)
(nil))
Setting of register d3 is actually done in insns 31 . (set (reg:DI 2 d2)
Since this is in DI mode it is using d2 and d3 in DI mode.Similary d0
and a4 is accessed in DI mode. So d1 and a5 is also being used in this
insns.Hence negations is proper.
Just like Mike pointed out 95 tries to use [a4+4] but insn 94
clobbered a4 already.
The compiler should actually generate insn similar to insn 91 and 92
in between insn 94 and 95, but not using a4,or after saving a4. This
is not happening. Insn 90 to 94 are emitted only from greg pass
onwards.
When i inserted the necessary assembly instructions correspoinding to
movsi_short_const and addsi3 between insns 91 and 92 in the assemble
file , the program worked fine.
There are spill codes for insns 31 in the beginning of the the .greg
file but i cant understand anything of that.
Spilling for insn 31.
Using reg 2 for reload 2
Using reg 12 for reload 3
Using reg 13 for reload 0
Using reg 13 for reload 1
The same program works for gcc 3.2 and gcc3.4.6 ports of the same private target
I am not sure whether this is because of reload pass or global
register allocation.
1. What could be the reason for this behavior?
2. How to overcome this type of behavior
Regards,
Shafi