Re: Modifying ARM code generator for elimination of 8bit writes - need help

[Paul Brook <paul at codesourcery dot com>]

> > (define_insn "*arm_movqi_insn"
> >   [(set (match_operand:QI 0 "nonimmediate_operand" "=r,r,r,Q")
> > 	(match_operand:QI 1 "general_operand" "rI,K,m,+r"))]
> Changing "m" to "Q", narrowing the address modes
> Changing "r" to "+r", (register is globbered)

This is wrong. the "+" applies to the operand, not the individual alternative 
(thus should go at the start of the constraint string).

Also, I doubt you can just say "movqi clobbers its input".

I expect you still have to effectively do the same as if you were doing a 
read-modify-write implementation. Otherwise reload will get very upset with 
you. swpb effectively just implements that in a single instruction rather 
than having to do it manually.
See the alpha backend for an example of how this can be implemented.

Paul