This is the mail archive of the gcc@gcc.gnu.org mailing list for the GCC project.


Index Nav: [Date Index] [Subject Index] [Author Index] [Thread Index]
Message Nav: [Date Prev] [Date Next] [Thread Prev] [Thread Next]
Other format: [Raw text]

Re: Scheduler questions (related to PR17808)


On Thursday 30 June 2005 16:19, Mostafa Hagog wrote:
> Hi,
>
> Steven Bosscher <stevenb@suse.de> wrote on 30/06/2005 01:46:22:
> > Hi,
>
> [snip]
>
> > Then the ia64 machine-reorg scheduler gets to work, and it produces:
> >
> > (insn:TI 8 70 12 0 (set (reg:BI 262 p6 [353])
> >         (ne:BI (reg/v:SI 15 r15 [orig:348 b1 ] [348])
> >             (const_int 0 [0x0]))) 226 {*cmpsi_normal}
>
> (insn_list:REG_DEP_TRUE 7 (nil))
>
> >     (nil))
> >
> > (jump_insn 12 8 77 0 (set (pc)
> >         (if_then_else (eq (reg:BI 262 p6 [353])
> >                 (const_int 0 [0x0]))
> >             (label_ref:DI 39)
>
>                          ^^^^^
> It would help to know what is the target of this jump;
> If it is bb1 then the move of the insn 14 above 9 and 10
> is legal because the predicate doesn't hold for them.
> I am not sure if the scheduler is that smart to make such
> decisions but it would help to get all of the RTL to get
> the full picture.

I have attached the full .mach dump from which I quoted.

Gr.
Steven

Attachment: t.c.35.mach.gz
Description: GNU Zip compressed data


Index Nav: [Date Index] [Subject Index] [Author Index] [Thread Index]
Message Nav: [Date Prev] [Date Next] [Thread Prev] [Thread Next]