Re: Help with constraint for single register

[Robert Baruch <autophile at gmail dot com>]

:(

That darn W register is getting in the way everywhere. Here's an insn
that appears before the CSE pass:

(insn 457 456 458 0 ../../Desktop/gcc-3.4.3/gcc/libgcc2.c:462 (set:QI
(reg:QI 71)
        (reg:QI 0 W)) -1 (nil)
    (expr_list:REG_EQUAL (plus:QI (reg/f:QI 49 R20/FP)
            (const_int 32 [0x20]))
        (nil)))


I guess this means W -> pseudo-71, where pseudo-71 is equal to R20 + 32.

But after the CSE pass, that insn turns into:

(insn 457 456 458 0 ../../Desktop/gcc-3.4.3/gcc/libgcc2.c:462 (set:QI
(reg:QI 71)
        (plus:QI (reg/f:QI 49 R20/FP)
            (const_int 32 [0x20]))) 1 {*addqi3} (nil)
    (expr_list:REG_EQUAL (plus:QI (reg/f:QI 49 R20/FP)
            (const_int 32 [0x20]))
        (nil)))

So R20 + 32 -> pseudo-71.

The strange thing is that apparently CSE has recognized this as an
*addqi3 template, which doesn't make sense because this is that
template:

(define_insn "*addqi3"
	[(set (match_operand:QI 0 "register_operand" "=r,W,W")
		  (plus:QI (match_operand:QI 1 "register_operand" "%0,0,0")
                   (match_operand:QI 2 "nonmemory_operand" "W,r,i")))]
  ""
  "\taddf %0,%2"
  [(set_attr "cc" "all")]
  )

Where "W" means the W register. There is no way that *addqi3 could
match the insn.

QUESTION #1: Why is the CSE pass putting {*addqi3} in the insn?
QUESTION #2: How do I force the CSE pass, or any future pass to obey
my restriction that all adds must take place through the W register?

Thanks for any help,

--Rob