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Re: SPE scalar float instructions

From: Kumar Gala <kumar dot gala at freescale dot com>
To: "Zack Weinberg" <zack at codesourcery dot com>
Cc: <gcc at gcc dot gnu dot org>, "Aldy Hernandez" <aldyh at redhat dot com>
Date: Wed, 15 Dec 2004 09:23:44 -0600
Subject: Re: SPE scalar float instructions
References: <87wtvkb52c.fsf@codesourcery.com>

Zack,

Not sure what TARGET_SPE implies (Aldy should know :)

However, we did want to keep the SPE scalar float usage separate from the SPE vector instructions. Its feasible and possible that Freescale may release a processor that implements only the scalar floating point instructions and not the SIMD instructions.

- kumar

On Dec 14, 2004, at 9:42 PM, Zack Weinberg wrote:

Currently, the SPE scalar float instructions are predicated on
 TARGET_HARD_FLOAT && !TARGET_FPRS (and TARGET_E500_DOUBLE for DFmode)
 but not on TARGET_SPE.? This can cause problems in an embedded context
 - as one of CodeSourcery's customers points out,
> This will indeed post a problem, because those instructions require > MSR[SPE] bit be set, which is not true for all cases.? SPE unavailable > exception may result.
I'm wondering if TARGET_SPE should be added to the controlling
 condition for all those instructions.? Thoughts?
zw

References:
- SPE scalar float instructions
  - From: Zack Weinberg

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