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Re: heads up new sub-port e500 v2
On Thu, Oct 21, 2004 at 06:06:21AM -0700, Geoff Keating wrote:
> It would depend on the exact changes, could you post a patch?
I'm in the midst of cleaning up the changes because of bit-rot, etc.
Here is an -old- patch I have lying around, not the latest which I'm
working on.
Could you take a look at it, and let me know if it's generally ok?
I think the config.gcc and documentation changes are not in this current
patch, but in my local tree. Anywhooo... you'll get the idea.
Again...this is an old patch that I'm revamping. This is NOT what I
plan to submit.
Cheers.
Aldy
2004-10-19 Aldy Hernandez <aldyh@redhat.com>
* config.gcc: Add support for --enable-e500_double.
* config/rs6000/e500-double.h: New file.
* config/rs6000/rs6000.h: Define TARGET_E500_SINGLE and
TARGET_E500_DOUBLE.
* config/rs6000/eabi.h: Define TARGET_E500_SINGLE and
TARGET_E500_DOUBLE.
* config/rs6000/linuxspe.h: Same.
* doc/invoke.texi (Option Summary): Document new options for
mfloat-gprs.
(RS/6000 and PowerPC Options): Same.
* config/rs6000/rs6000.c (rs6000_parse_float_gprs_option): New
function.
(rs6000_override_options): Use it. Use
SUB3TARGET_OVERRIDE_OPTIONS.
(rs6000_legitimate_address): Handle e500 doubles.
(rs6000_legitimize_address): Same.
(rs6000_legitimize_reload_address): Same.
(rs6000_hard_regno_nregs): Same.
(spe_func_has_64bit_regs_p): Same.
(emit_frame_save): Same.
(gen_frame_mem_offset): Same.
(rs6000_dwarf_register_span): Same.
(rs6000_generate_compare): Same.
(easy_fp_constant): Same.
(legitimate_offset_address_p): Same.
* config/rs6000/spe.md: (cmdfeq_gpr): New.
(tstdfeq_gpr): New.
(cmpdfgt_gpr): New.
(tstdfgt_gpr): New.
(tstdfgt_gpr): New.
(cmpdflt_gpr): New.
(tstdflt_gpr): New.
Add new constants.
2004-04-30 Aldy Hernandez <aldyh@redhat.com>
* config/rs6000/rs6000.md ("extendsfdf2"): New expander.
("fpr_extendsfdf2"): Rename from extendsfdf2.
("movdf_softfloat32"): Key off of TARGET_E500_SINGLE.
(truncdfsf2): Rewrite as expander.
(fpr_truncdfsf2): New.
(absdf2): Rewrite as expander.
(fpr_absdf2): New.
(fpr_nabsdf2): Name pattern.
(negdf2): Rewrite as expander.
(fpr_negdf2): New.
(adddf3): Rewrite as expander.
(fpr_adddf3): New.
(subdf3): Rewrite as expander.
(fpr_subdf3): New.
(muldf3): Rewrite as expander.
(fpr_muldf3): New.
(cmpdf): Allow for TARGET_E500_DOUBLE.
(fixuns_truncdfsi2): New.
* config/rs6000/spe.md ("spe_extendsfdf2"): New.
("movdf_e500_double"): New.
(spe_truncdfsf2): New.
(spe_absdf2): New.
(spe_nabsdf2): New.
(spe_negdf2): New.
(sub_adddf3): New.
(spe_subdf3): New.
(spe_muldf3): New.
(spe_floatsidf2): New.
(spe_floatunssidf2): New.
(spe_fix_truncdfsi2): New.
(spe_fixuns_truncdfsi2): New.
Index: e500-double.h
===================================================================
RCS file: e500-double.h
diff -N e500-double.h
*** /dev/null 1 Jan 1970 00:00:00 -0000
--- e500-double.h 13 May 2004 11:53:53 -0000
***************
*** 0 ****
--- 1,25 ----
+ /* Target definitions for E500 with double precision FP.
+ Copyright (C) 2004 Free Software Foundation, Inc.
+ Contributed by Aldy Hernandez (aldyh@redhat.com).
+
+ This file is part of GCC.
+
+ GCC is free software; you can redistribute it and/or modify it
+ under the terms of the GNU General Public License as published
+ by the Free Software Foundation; either version 2, or (at your
+ option) any later version.
+
+ GCC is distributed in the hope that it will be useful, but WITHOUT
+ ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
+ or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public
+ License for more details.
+
+ You should have received a copy of the GNU General Public License
+ along with GCC; see the file COPYING. If not, write to the
+ Free Software Foundation, 59 Temple Place - Suite 330, Boston,
+ MA 02111-1307, USA. */
+
+ #undef SUB3TARGET_OVERRIDE_OPTIONS
+ #define SUB3TARGET_OVERRIDE_OPTIONS \
+ if (rs6000_float_gprs_string == NULL) \
+ rs6000_float_gprs = 2;
Index: eabi.h
===================================================================
RCS file: /cvs/gcc/gcc/gcc/config/rs6000/eabi.h,v
retrieving revision 1.11
diff -c -p -r1.11 eabi.h
*** eabi.h 10 Jun 2003 16:01:39 -0000 1.11
--- eabi.h 13 May 2004 11:53:54 -0000
***************
*** 49,57 ****
#undef TARGET_E500
#undef TARGET_ISEL
#undef TARGET_FPRS
#define TARGET_SPE_ABI rs6000_spe_abi
#define TARGET_SPE rs6000_spe
#define TARGET_E500 (rs6000_cpu == PROCESSOR_PPC8540)
#define TARGET_ISEL rs6000_isel
! #define TARGET_FPRS (!rs6000_float_gprs)
--- 49,61 ----
#undef TARGET_E500
#undef TARGET_ISEL
#undef TARGET_FPRS
+ #undef TARGET_E500_SINGLE
+ #undef TARGET_E500_DOUBLE
#define TARGET_SPE_ABI rs6000_spe_abi
#define TARGET_SPE rs6000_spe
#define TARGET_E500 (rs6000_cpu == PROCESSOR_PPC8540)
#define TARGET_ISEL rs6000_isel
! #define TARGET_FPRS (rs6000_float_gprs == 0)
! #define TARGET_E500_SINGLE (TARGET_HARD_FLOAT && rs6000_float_gprs == 1)
! #define TARGET_E500_DOUBLE (TARGET_HARD_FLOAT && rs6000_float_gprs == 2)
Index: linuxspe.h
===================================================================
RCS file: /cvs/gcc/gcc/gcc/config/rs6000/linuxspe.h,v
retrieving revision 1.2
diff -c -p -r1.2 linuxspe.h
*** linuxspe.h 5 Oct 2003 22:49:29 -0000 1.2
--- linuxspe.h 13 May 2004 11:53:54 -0000
***************
*** 32,43 ****
#undef TARGET_E500
#undef TARGET_ISEL
#undef TARGET_FPRS
#define TARGET_SPE_ABI rs6000_spe_abi
#define TARGET_SPE rs6000_spe
#define TARGET_E500 (rs6000_cpu == PROCESSOR_PPC8540)
#define TARGET_ISEL rs6000_isel
! #define TARGET_FPRS (!rs6000_float_gprs)
#undef SUBSUBTARGET_OVERRIDE_OPTIONS
#define SUBSUBTARGET_OVERRIDE_OPTIONS \
--- 32,47 ----
#undef TARGET_E500
#undef TARGET_ISEL
#undef TARGET_FPRS
+ #undef TARGET_E500_SINGLE
+ #undef TARGET_E500_DOUBLE
#define TARGET_SPE_ABI rs6000_spe_abi
#define TARGET_SPE rs6000_spe
#define TARGET_E500 (rs6000_cpu == PROCESSOR_PPC8540)
#define TARGET_ISEL rs6000_isel
! #define TARGET_FPRS (rs6000_float_gprs == 0)
! #define TARGET_E500_SINGLE (TARGET_HARD_FLOAT && rs6000_float_gprs == 1)
! #define TARGET_E500_DOUBLE (TARGET_HARD_FLOAT && rs6000_float_gprs == 2)
#undef SUBSUBTARGET_OVERRIDE_OPTIONS
#define SUBSUBTARGET_OVERRIDE_OPTIONS \
Index: rs6000.c
===================================================================
RCS file: /cvs/gcc/gcc/gcc/config/rs6000/rs6000.c,v
retrieving revision 1.642
diff -c -p -r1.642 rs6000.c
*** rs6000.c 13 May 2004 06:40:04 -0000 1.642
--- rs6000.c 13 May 2004 11:54:01 -0000
*************** static void rs6000_parse_abi_options (vo
*** 406,411 ****
--- 406,412 ----
static void rs6000_parse_alignment_option (void);
static void rs6000_parse_tls_size_option (void);
static void rs6000_parse_yes_no_option (const char *, const char *, int *);
+ static void rs6000_parse_float_gprs_option (void);
static int first_altivec_reg_to_save (void);
static unsigned int compute_vrsave_mask (void);
static void is_altivec_return_reg (rtx, void *);
*************** rs6000_override_options (const char *def
*** 928,933 ****
--- 929,936 ----
/* Handle -mabi= options. */
rs6000_parse_abi_options ();
+ rs6000_parse_float_gprs_option ();
+
/* Handle -malign-XXXXX option. */
rs6000_parse_alignment_option ();
*************** rs6000_override_options (const char *def
*** 937,944 ****
rs6000_parse_yes_no_option ("isel", rs6000_isel_string,
&rs6000_isel);
rs6000_parse_yes_no_option ("spe", rs6000_spe_string, &rs6000_spe);
- rs6000_parse_yes_no_option ("float-gprs", rs6000_float_gprs_string,
- &rs6000_float_gprs);
/* Handle -mtls-size option. */
rs6000_parse_tls_size_option ();
--- 940,945 ----
*************** rs6000_override_options (const char *def
*** 949,954 ****
--- 950,958 ----
#ifdef SUBSUBTARGET_OVERRIDE_OPTIONS
SUBSUBTARGET_OVERRIDE_OPTIONS;
#endif
+ #ifdef SUB3TARGET_OVERRIDE_OPTIONS
+ SUB3TARGET_OVERRIDE_OPTIONS;
+ #endif
if (TARGET_E500)
{
*************** rs6000_parse_abi_options (void)
*** 1147,1152 ****
--- 1151,1173 ----
error ("unknown ABI specified: '%s'", rs6000_abi_string);
}
+ /* Handle -mfloat-gprs= options. */
+ static void
+ rs6000_parse_float_gprs_option (void)
+ {
+ if (rs6000_float_gprs_string == 0)
+ return;
+ else if (! strcmp (rs6000_float_gprs_string, "yes")
+ || ! strcmp (rs6000_float_gprs_string, "single"))
+ rs6000_float_gprs = 1;
+ else if (! strcmp (rs6000_float_gprs_string, "double"))
+ rs6000_float_gprs = 2;
+ else if (! strcmp (rs6000_float_gprs_string, "no"))
+ rs6000_float_gprs = 0;
+ else
+ error ("invalid option for -mfloat-gprs");
+ }
+
/* Handle -malign-XXXXXX options. */
static void
rs6000_parse_alignment_option (void)
*************** easy_fp_constant (rtx op, enum machine_m
*** 1674,1680 ****
return 0;
/* Consider all constants with -msoft-float to be easy. */
! if ((TARGET_SOFT_FLOAT || !TARGET_FPRS)
&& mode != DImode)
return 1;
--- 1695,1701 ----
return 0;
/* Consider all constants with -msoft-float to be easy. */
! if ((TARGET_SOFT_FLOAT || TARGET_E500_SINGLE)
&& mode != DImode)
return 1;
*************** easy_fp_constant (rtx op, enum machine_m
*** 1708,1713 ****
--- 1729,1737 ----
long k[2];
REAL_VALUE_TYPE rv;
+ if (TARGET_E500_DOUBLE)
+ return 0;
+
REAL_VALUE_FROM_CONST_DOUBLE (rv, op);
REAL_VALUE_TO_TARGET_DOUBLE (rv, k);
*************** legitimate_offset_address_p (enum machin
*** 2674,2679 ****
--- 2698,2706 ----
return SPE_CONST_OFFSET_OK (offset);
case DFmode:
+ if (TARGET_E500_DOUBLE)
+ return SPE_CONST_OFFSET_OK (offset);
+
case DImode:
if (mode == DFmode || !TARGET_POWERPC64)
extra = 4;
*************** rs6000_legitimize_address (rtx x, rtx ol
*** 2826,2832 ****
&& GET_MODE_NUNITS (mode) == 1
&& ((TARGET_HARD_FLOAT && TARGET_FPRS)
|| TARGET_POWERPC64
! || (mode != DFmode && mode != TFmode))
&& (TARGET_POWERPC64 || mode != DImode)
&& mode != TImode)
{
--- 2853,2859 ----
&& GET_MODE_NUNITS (mode) == 1
&& ((TARGET_HARD_FLOAT && TARGET_FPRS)
|| TARGET_POWERPC64
! || ((mode != DFmode || TARGET_E500_DOUBLE) && mode != TFmode))
&& (TARGET_POWERPC64 || mode != DImode)
&& mode != TImode)
{
*************** rs6000_legitimize_address (rtx x, rtx ol
*** 2845,2851 ****
reg = force_reg (Pmode, x);
return reg;
}
! else if (SPE_VECTOR_MODE (mode))
{
/* We accept [reg + reg] and [reg + OFFSET]. */
--- 2872,2879 ----
reg = force_reg (Pmode, x);
return reg;
}
! else if (SPE_VECTOR_MODE (mode)
! || (mode == DFmode && TARGET_E500_DOUBLE))
{
/* We accept [reg + reg] and [reg + OFFSET]. */
*************** rs6000_legitimize_address (rtx x, rtx ol
*** 2889,2895 ****
&& GET_CODE (x) != CONST_INT
&& GET_CODE (x) != CONST_DOUBLE
&& CONSTANT_P (x)
! && ((TARGET_HARD_FLOAT && TARGET_FPRS) || mode != DFmode)
&& mode != DImode
&& mode != TImode)
{
--- 2917,2924 ----
&& GET_CODE (x) != CONST_INT
&& GET_CODE (x) != CONST_DOUBLE
&& CONSTANT_P (x)
! && ((TARGET_HARD_FLOAT && TARGET_FPRS)
! || (mode != DFmode || TARGET_E500_DOUBLE))
&& mode != DImode
&& mode != TImode)
{
*************** rs6000_legitimize_reload_address (rtx x,
*** 3236,3241 ****
--- 3265,3271 ----
&& REG_MODE_OK_FOR_BASE_P (XEXP (x, 0), mode)
&& GET_CODE (XEXP (x, 1)) == CONST_INT
&& !SPE_VECTOR_MODE (mode)
+ && !(TARGET_E500_DOUBLE && mode == DFmode)
&& !ALTIVEC_VECTOR_MODE (mode))
{
HOST_WIDE_INT val = INTVAL (XEXP (x, 1));
*************** rs6000_legitimate_address (enum machine_
*** 3332,3337 ****
--- 3362,3368 ----
if ((GET_CODE (x) == PRE_INC || GET_CODE (x) == PRE_DEC)
&& !ALTIVEC_VECTOR_MODE (mode)
&& !SPE_VECTOR_MODE (mode)
+ && !(TARGET_E500_DOUBLE && mode == DFmode)
&& TARGET_UPDATE
&& legitimate_indirect_address_p (XEXP (x, 0), reg_ok_strict))
return 1;
*************** rs6000_legitimate_address (enum machine_
*** 3352,3358 ****
if (mode != TImode
&& ((TARGET_HARD_FLOAT && TARGET_FPRS)
|| TARGET_POWERPC64
! || (mode != DFmode && mode != TFmode))
&& (TARGET_POWERPC64 || mode != DImode)
&& legitimate_indexed_address_p (x, reg_ok_strict))
return 1;
--- 3383,3389 ----
if (mode != TImode
&& ((TARGET_HARD_FLOAT && TARGET_FPRS)
|| TARGET_POWERPC64
! || ((mode != DFmode || TARGET_E500_DOUBLE) && mode != TFmode))
&& (TARGET_POWERPC64 || mode != DImode)
&& legitimate_indexed_address_p (x, reg_ok_strict))
return 1;
*************** rs6000_hard_regno_nregs (int regno, enum
*** 3417,3422 ****
--- 3448,3456 ----
if (FP_REGNO_P (regno))
return (GET_MODE_SIZE (mode) + UNITS_PER_FP_WORD - 1) / UNITS_PER_FP_WORD;
+ if (TARGET_E500_DOUBLE && mode == DFmode)
+ return 1;
+
if (SPE_SIMD_REGNO_P (regno) && TARGET_SPE && SPE_VECTOR_MODE (mode))
return (GET_MODE_SIZE (mode) + UNITS_PER_SPE_WORD - 1) / UNITS_PER_SPE_WORD;
*************** rs6000_generate_compare (enum rtx_code c
*** 10018,10023 ****
--- 10052,10062 ----
&& rs6000_compare_fp_p)
{
rtx cmp, or1, or2, or_result, compare_result2;
+ enum machine_mode op_mode;
+
+ op_mode = GET_MODE (rs6000_compare_op0);
+ if (op_mode == VOIDmode)
+ op_mode = GET_MODE (rs6000_compare_op1);
/* Note: The E500 comparison instructions set the GT bit (x +
1), on success. This explains the mess. */
*************** rs6000_generate_compare (enum rtx_code c
*** 10025,10049 ****
switch (code)
{
case EQ: case UNEQ: case NE: case LTGT:
! cmp = flag_finite_math_only
! ? gen_tstsfeq_gpr (compare_result, rs6000_compare_op0,
! rs6000_compare_op1)
! : gen_cmpsfeq_gpr (compare_result, rs6000_compare_op0,
! rs6000_compare_op1);
break;
case GT: case GTU: case UNGT: case UNGE: case GE: case GEU:
! cmp = flag_finite_math_only
! ? gen_tstsfgt_gpr (compare_result, rs6000_compare_op0,
! rs6000_compare_op1)
! : gen_cmpsfgt_gpr (compare_result, rs6000_compare_op0,
! rs6000_compare_op1);
break;
case LT: case LTU: case UNLT: case UNLE: case LE: case LEU:
! cmp = flag_finite_math_only
! ? gen_tstsflt_gpr (compare_result, rs6000_compare_op0,
! rs6000_compare_op1)
! : gen_cmpsflt_gpr (compare_result, rs6000_compare_op0,
! rs6000_compare_op1);
break;
default:
abort ();
--- 10064,10112 ----
switch (code)
{
case EQ: case UNEQ: case NE: case LTGT:
! if (op_mode == SFmode)
! cmp = flag_finite_math_only
! ? gen_tstsfeq_gpr (compare_result, rs6000_compare_op0,
! rs6000_compare_op1)
! : gen_cmpsfeq_gpr (compare_result, rs6000_compare_op0,
! rs6000_compare_op1);
! else if (op_mode == DFmode)
! cmp = flag_finite_math_only
! ? gen_tstdfeq_gpr (compare_result, rs6000_compare_op0,
! rs6000_compare_op1)
! : gen_cmpdfeq_gpr (compare_result, rs6000_compare_op0,
! rs6000_compare_op1);
! else abort ();
break;
case GT: case GTU: case UNGT: case UNGE: case GE: case GEU:
! if (op_mode == SFmode)
! cmp = flag_finite_math_only
! ? gen_tstsfgt_gpr (compare_result, rs6000_compare_op0,
! rs6000_compare_op1)
! : gen_cmpsfgt_gpr (compare_result, rs6000_compare_op0,
! rs6000_compare_op1);
! else if (op_mode == DFmode)
! cmp = flag_finite_math_only
! ? gen_tstdfgt_gpr (compare_result, rs6000_compare_op0,
! rs6000_compare_op1)
! : gen_cmpdfgt_gpr (compare_result, rs6000_compare_op0,
! rs6000_compare_op1);
! else abort ();
break;
case LT: case LTU: case UNLT: case UNLE: case LE: case LEU:
! if (op_mode == SFmode)
! cmp = flag_finite_math_only
! ? gen_tstsflt_gpr (compare_result, rs6000_compare_op0,
! rs6000_compare_op1)
! : gen_cmpsflt_gpr (compare_result, rs6000_compare_op0,
! rs6000_compare_op1);
! else if (op_mode == DFmode)
! cmp = flag_finite_math_only
! ? gen_tstdflt_gpr (compare_result, rs6000_compare_op0,
! rs6000_compare_op1)
! : gen_cmpdflt_gpr (compare_result, rs6000_compare_op0,
! rs6000_compare_op1);
! else abort ();
break;
default:
abort ();
*************** rs6000_generate_compare (enum rtx_code c
*** 10069,10079 ****
compare_result2 = gen_reg_rtx (CCFPmode);
/* Do the EQ. */
! cmp = flag_finite_math_only
! ? gen_tstsfeq_gpr (compare_result2, rs6000_compare_op0,
! rs6000_compare_op1)
! : gen_cmpsfeq_gpr (compare_result2, rs6000_compare_op0,
! rs6000_compare_op1);
emit_insn (cmp);
or1 = gen_rtx_GT (SImode, compare_result, const0_rtx);
--- 10132,10150 ----
compare_result2 = gen_reg_rtx (CCFPmode);
/* Do the EQ. */
! if (op_mode == SFmode)
! cmp = flag_finite_math_only
! ? gen_tstsfeq_gpr (compare_result2, rs6000_compare_op0,
! rs6000_compare_op1)
! : gen_cmpsfeq_gpr (compare_result2, rs6000_compare_op0,
! rs6000_compare_op1);
! else if (op_mode == DFmode)
! cmp = flag_finite_math_only
! ? gen_tstdfeq_gpr (compare_result2, rs6000_compare_op0,
! rs6000_compare_op1)
! : gen_cmpdfeq_gpr (compare_result2, rs6000_compare_op0,
! rs6000_compare_op1);
! else abort ();
emit_insn (cmp);
or1 = gen_rtx_GT (SImode, compare_result, const0_rtx);
*************** spe_func_has_64bit_regs_p (void)
*** 11279,11287 ****
rtx i;
i = PATTERN (insn);
! if (GET_CODE (i) == SET
! && SPE_VECTOR_MODE (GET_MODE (SET_SRC (i))))
! return true;
}
}
--- 11350,11364 ----
rtx i;
i = PATTERN (insn);
! if (GET_CODE (i) == SET)
! {
! enum machine_mode mode = GET_MODE (SET_SRC (i));
!
! if (SPE_VECTOR_MODE (mode))
! return true;
! if (TARGET_E500_DOUBLE && mode == DFmode)
! return true;
! }
}
}
*************** emit_frame_save (rtx frame_reg, rtx fram
*** 12098,12103 ****
--- 12175,12181 ----
/* Some cases that need register indexed addressing. */
if ((TARGET_ALTIVEC_ABI && ALTIVEC_VECTOR_MODE (mode))
+ || (TARGET_E500_DOUBLE && mode == DFmode)
|| (TARGET_SPE_ABI
&& SPE_VECTOR_MODE (mode)
&& !SPE_CONST_OFFSET_OK (offset)))
*************** gen_frame_mem_offset (enum machine_mode
*** 12137,12143 ****
int_rtx = GEN_INT (offset);
! if (TARGET_SPE_ABI && SPE_VECTOR_MODE (mode))
{
offset_rtx = gen_rtx_REG (Pmode, FIXED_SCRATCH);
emit_move_insn (offset_rtx, int_rtx);
--- 12215,12222 ----
int_rtx = GEN_INT (offset);
! if ((TARGET_SPE_ABI && SPE_VECTOR_MODE (mode))
! || (TARGET_E500_DOUBLE && mode == DFmode))
{
offset_rtx = gen_rtx_REG (Pmode, FIXED_SCRATCH);
emit_move_insn (offset_rtx, int_rtx);
*************** rs6000_dwarf_register_span (rtx reg)
*** 16484,16491 ****
{
unsigned regno;
! if (!TARGET_SPE || !SPE_VECTOR_MODE (GET_MODE (reg)))
! return NULL_RTX;
regno = REGNO (reg);
--- 16563,16574 ----
{
unsigned regno;
! if (!TARGET_SPE)
! {
! if (!SPE_VECTOR_MODE (GET_MODE (reg))
! && !(TARGET_E500_DOUBLE && GET_MODE (reg) == DFmode))
! return NULL_RTX;
! }
regno = REGNO (reg);
Index: rs6000.h
===================================================================
RCS file: /cvs/gcc/gcc/gcc/config/rs6000/rs6000.h,v
retrieving revision 1.324
diff -c -p -r1.324 rs6000.h
*** rs6000.h 9 May 2004 14:32:49 -0000 1.324
--- rs6000.h 13 May 2004 11:54:03 -0000
*************** extern const char *rs6000_warn_altivec_l
*** 560,565 ****
--- 560,567 ----
#define TARGET_E500 0
#define TARGET_ISEL 0
#define TARGET_FPRS 1
+ #define TARGET_E500_SINGLE 0
+ #define TARGET_E500_DOUBLE 0
/* Sometimes certain combinations of command options do not make sense
on a particular target machine. You can define a macro
Index: rs6000.md
===================================================================
RCS file: /cvs/gcc/gcc/gcc/config/rs6000/rs6000.md,v
retrieving revision 1.304
diff -c -p -r1.304 rs6000.md
*** rs6000.md 28 Apr 2004 23:03:28 -0000 1.304
--- rs6000.md 13 May 2004 11:54:06 -0000
***************
*** 4372,4378 ****
;; this case, we just lose precision that we would have otherwise gotten but
;; is not guaranteed. Perhaps this should be tightened up at some point.
! (define_insn "extendsfdf2"
[(set (match_operand:DF 0 "gpc_reg_operand" "=f")
(float_extend:DF (match_operand:SF 1 "gpc_reg_operand" "f")))]
"TARGET_HARD_FLOAT && TARGET_FPRS"
--- 4372,4384 ----
;; this case, we just lose precision that we would have otherwise gotten but
;; is not guaranteed. Perhaps this should be tightened up at some point.
! (define_expand "extendsfdf2"
! [(set (match_operand:DF 0 "gpc_reg_operand" "")
! (float_extend:DF (match_operand:SF 1 "gpc_reg_operand" "")))]
! "TARGET_HARD_FLOAT && (TARGET_FPRS || TARGET_E500_DOUBLE)"
! "")
!
! (define_insn "fpr_extendsfdf2"
[(set (match_operand:DF 0 "gpc_reg_operand" "=f")
(float_extend:DF (match_operand:SF 1 "gpc_reg_operand" "f")))]
"TARGET_HARD_FLOAT && TARGET_FPRS"
***************
*** 4385,4391 ****
}"
[(set_attr "type" "fp")])
! (define_insn "truncdfsf2"
[(set (match_operand:SF 0 "gpc_reg_operand" "=f")
(float_truncate:SF (match_operand:DF 1 "gpc_reg_operand" "f")))]
"TARGET_HARD_FLOAT && TARGET_FPRS"
--- 4391,4403 ----
}"
[(set_attr "type" "fp")])
! (define_expand "truncdfsf2"
! [(set (match_operand:SF 0 "gpc_reg_operand" "")
! (float_truncate:SF (match_operand:DF 1 "gpc_reg_operand" "")))]
! "TARGET_HARD_FLOAT && (TARGET_FPRS || TARGET_E500_DOUBLE)"
! "")
!
! (define_insn "fpr_truncdfsf2"
[(set (match_operand:SF 0 "gpc_reg_operand" "=f")
(float_truncate:SF (match_operand:DF 1 "gpc_reg_operand" "f")))]
"TARGET_HARD_FLOAT && TARGET_FPRS"
***************
*** 4775,4802 ****
"fsel %0,%1,%2,%3"
[(set_attr "type" "fp")])
! (define_insn "negdf2"
[(set (match_operand:DF 0 "gpc_reg_operand" "=f")
(neg:DF (match_operand:DF 1 "gpc_reg_operand" "f")))]
"TARGET_HARD_FLOAT && TARGET_FPRS"
"fneg %0,%1"
[(set_attr "type" "fp")])
! (define_insn "absdf2"
[(set (match_operand:DF 0 "gpc_reg_operand" "=f")
(abs:DF (match_operand:DF 1 "gpc_reg_operand" "f")))]
"TARGET_HARD_FLOAT && TARGET_FPRS"
"fabs %0,%1"
[(set_attr "type" "fp")])
! (define_insn ""
[(set (match_operand:DF 0 "gpc_reg_operand" "=f")
(neg:DF (abs:DF (match_operand:DF 1 "gpc_reg_operand" "f"))))]
"TARGET_HARD_FLOAT && TARGET_FPRS"
"fnabs %0,%1"
[(set_attr "type" "fp")])
! (define_insn "adddf3"
[(set (match_operand:DF 0 "gpc_reg_operand" "=f")
(plus:DF (match_operand:DF 1 "gpc_reg_operand" "%f")
(match_operand:DF 2 "gpc_reg_operand" "f")))]
--- 4787,4833 ----
"fsel %0,%1,%2,%3"
[(set_attr "type" "fp")])
! (define_expand "negdf2"
! [(set (match_operand:DF 0 "gpc_reg_operand" "")
! (neg:DF (match_operand:DF 1 "gpc_reg_operand" "")))]
! "TARGET_HARD_FLOAT && (TARGET_FPRS || TARGET_E500_DOUBLE)"
! "")
!
! (define_insn "fpr_negdf2"
[(set (match_operand:DF 0 "gpc_reg_operand" "=f")
(neg:DF (match_operand:DF 1 "gpc_reg_operand" "f")))]
"TARGET_HARD_FLOAT && TARGET_FPRS"
"fneg %0,%1"
[(set_attr "type" "fp")])
! (define_expand "absdf2"
! [(set (match_operand:DF 0 "gpc_reg_operand" "")
! (abs:DF (match_operand:DF 1 "gpc_reg_operand" "")))]
! "TARGET_HARD_FLOAT && (TARGET_FPRS || TARGET_E500_DOUBLE)"
! "")
!
! (define_insn "fpr_absdf2"
[(set (match_operand:DF 0 "gpc_reg_operand" "=f")
(abs:DF (match_operand:DF 1 "gpc_reg_operand" "f")))]
"TARGET_HARD_FLOAT && TARGET_FPRS"
"fabs %0,%1"
[(set_attr "type" "fp")])
! (define_insn "fpr_nabsdf2"
[(set (match_operand:DF 0 "gpc_reg_operand" "=f")
(neg:DF (abs:DF (match_operand:DF 1 "gpc_reg_operand" "f"))))]
"TARGET_HARD_FLOAT && TARGET_FPRS"
"fnabs %0,%1"
[(set_attr "type" "fp")])
! (define_expand "adddf3"
! [(set (match_operand:DF 0 "gpc_reg_operand" "")
! (plus:DF (match_operand:DF 1 "gpc_reg_operand" "")
! (match_operand:DF 2 "gpc_reg_operand" "")))]
! "TARGET_HARD_FLOAT && (TARGET_FPRS || TARGET_E500_DOUBLE)"
! "")
!
! (define_insn "fpr_adddf3"
[(set (match_operand:DF 0 "gpc_reg_operand" "=f")
(plus:DF (match_operand:DF 1 "gpc_reg_operand" "%f")
(match_operand:DF 2 "gpc_reg_operand" "f")))]
***************
*** 4804,4810 ****
"{fa|fadd} %0,%1,%2"
[(set_attr "type" "fp")])
! (define_insn "subdf3"
[(set (match_operand:DF 0 "gpc_reg_operand" "=f")
(minus:DF (match_operand:DF 1 "gpc_reg_operand" "f")
(match_operand:DF 2 "gpc_reg_operand" "f")))]
--- 4835,4848 ----
"{fa|fadd} %0,%1,%2"
[(set_attr "type" "fp")])
! (define_expand "subdf3"
! [(set (match_operand:DF 0 "gpc_reg_operand" "")
! (minus:DF (match_operand:DF 1 "gpc_reg_operand" "")
! (match_operand:DF 2 "gpc_reg_operand" "")))]
! "TARGET_HARD_FLOAT && (TARGET_FPRS || TARGET_E500_DOUBLE)"
! "")
!
! (define_insn "fpr_subdf3"
[(set (match_operand:DF 0 "gpc_reg_operand" "=f")
(minus:DF (match_operand:DF 1 "gpc_reg_operand" "f")
(match_operand:DF 2 "gpc_reg_operand" "f")))]
***************
*** 4812,4818 ****
"{fs|fsub} %0,%1,%2"
[(set_attr "type" "fp")])
! (define_insn "muldf3"
[(set (match_operand:DF 0 "gpc_reg_operand" "=f")
(mult:DF (match_operand:DF 1 "gpc_reg_operand" "%f")
(match_operand:DF 2 "gpc_reg_operand" "f")))]
--- 4850,4863 ----
"{fs|fsub} %0,%1,%2"
[(set_attr "type" "fp")])
! (define_expand "muldf3"
! [(set (match_operand:DF 0 "gpc_reg_operand" "")
! (mult:DF (match_operand:DF 1 "gpc_reg_operand" "")
! (match_operand:DF 2 "gpc_reg_operand" "")))]
! "TARGET_HARD_FLOAT && (TARGET_FPRS || TARGET_E500_DOUBLE)"
! "")
!
! (define_insn "fpr_muldf3"
[(set (match_operand:DF 0 "gpc_reg_operand" "=f")
(mult:DF (match_operand:DF 1 "gpc_reg_operand" "%f")
(match_operand:DF 2 "gpc_reg_operand" "f")))]
***************
*** 4820,4826 ****
"{fm|fmul} %0,%1,%2"
[(set_attr "type" "dmul")])
! (define_insn "divdf3"
[(set (match_operand:DF 0 "gpc_reg_operand" "=f")
(div:DF (match_operand:DF 1 "gpc_reg_operand" "f")
(match_operand:DF 2 "gpc_reg_operand" "f")))]
--- 4865,4878 ----
"{fm|fmul} %0,%1,%2"
[(set_attr "type" "dmul")])
! (define_expand "divdf3"
! [(set (match_operand:DF 0 "gpc_reg_operand" "")
! (div:DF (match_operand:DF 1 "gpc_reg_operand" "")
! (match_operand:DF 2 "gpc_reg_operand" "")))]
! "TARGET_HARD_FLOAT && (TARGET_FPRS || TARGET_E500_DOUBLE)"
! "")
!
! (define_insn "fpr_divdf3"
[(set (match_operand:DF 0 "gpc_reg_operand" "=f")
(div:DF (match_operand:DF 1 "gpc_reg_operand" "f")
(match_operand:DF 2 "gpc_reg_operand" "f")))]
***************
*** 4969,4974 ****
--- 5021,5032 ----
"TARGET_HARD_FLOAT && !TARGET_FPRS"
"")
+ (define_expand "fixuns_truncdfsi2"
+ [(set (match_operand:SI 0 "gpc_reg_operand" "")
+ (unsigned_fix:SI (match_operand:DF 1 "gpc_reg_operand" "")))]
+ "TARGET_HARD_FLOAT && TARGET_E500_DOUBLE"
+ "")
+
(define_expand "fix_truncsfsi2"
[(set (match_operand:SI 0 "gpc_reg_operand" "")
(fix:SI (match_operand:SF 1 "gpc_reg_operand" "")))]
***************
*** 8126,8132 ****
(define_insn "*movdf_softfloat32"
[(set (match_operand:DF 0 "nonimmediate_operand" "=r,r,m,r,r,r")
(match_operand:DF 1 "input_operand" "r,m,r,G,H,F"))]
! "! TARGET_POWERPC64 && (TARGET_SOFT_FLOAT || !TARGET_FPRS)
&& (gpc_reg_operand (operands[0], DFmode)
|| gpc_reg_operand (operands[1], DFmode))"
"*
--- 8184,8190 ----
(define_insn "*movdf_softfloat32"
[(set (match_operand:DF 0 "nonimmediate_operand" "=r,r,m,r,r,r")
(match_operand:DF 1 "input_operand" "r,m,r,G,H,F"))]
! "! TARGET_POWERPC64 && (TARGET_SOFT_FLOAT || TARGET_E500_SINGLE)
&& (gpc_reg_operand (operands[0], DFmode)
|| gpc_reg_operand (operands[1], DFmode))"
"*
***************
*** 10905,10911 ****
(define_expand "cmpdf"
[(set (cc0) (compare (match_operand:DF 0 "gpc_reg_operand" "")
(match_operand:DF 1 "gpc_reg_operand" "")))]
! "TARGET_HARD_FLOAT && TARGET_FPRS"
"
{
rs6000_compare_op0 = operands[0];
--- 10963,10969 ----
(define_expand "cmpdf"
[(set (cc0) (compare (match_operand:DF 0 "gpc_reg_operand" "")
(match_operand:DF 1 "gpc_reg_operand" "")))]
! "TARGET_HARD_FLOAT && (TARGET_FPRS || TARGET_E500_DOUBLE)"
"
{
rs6000_compare_op0 = operands[0];
Index: spe.md
===================================================================
RCS file: /cvs/gcc/gcc/gcc/config/rs6000/spe.md,v
retrieving revision 1.24
diff -c -p -r1.24 spe.md
*** spe.md 11 May 2004 23:41:08 -0000 1.24
--- spe.md 13 May 2004 11:54:06 -0000
***************
*** 83,88 ****
--- 83,103 ----
"efsctuiz %0,%1"
[(set_attr "type" "fp")])
+ (define_insn "spe_fixuns_truncdfsi2"
+ [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
+ (unsigned_fix:SI (match_operand:DF 1 "gpc_reg_operand" "r")))]
+ "TARGET_HARD_FLOAT && TARGET_E500_DOUBLE"
+ "efdctuiz %0,%1"
+ [(set_attr "type" "fp")])
+
+ ;; Floating point conversions instructions.
+ (define_insn "spe_extendsfdf2"
+ [(set (match_operand:DF 0 "gpc_reg_operand" "=r")
+ (float_extend:DF (match_operand:SF 1 "gpc_reg_operand" "r")))]
+ "TARGET_HARD_FLOAT && TARGET_E500_DOUBLE"
+ "efdcfs %0,%1"
+ [(set_attr "type" "fp")])
+
(define_insn "spe_fix_truncsfsi2"
[(set (match_operand:SI 0 "gpc_reg_operand" "=r")
(fix:SI (match_operand:SF 1 "gpc_reg_operand" "r")))]
***************
*** 90,95 ****
--- 105,118 ----
"efsctsiz %0,%1"
[(set_attr "type" "fp")])
+ ;; FIXME fix expander.
+ (define_insn "spe_fix_truncdfsi2"
+ [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
+ (fix:SI (match_operand:DF 1 "gpc_reg_operand" "r")))]
+ "TARGET_HARD_FLOAT && TARGET_E500_DOUBLE"
+ "efdctsiz %0,%1"
+ [(set_attr "type" "fp")])
+
(define_insn "spe_floatunssisf2"
[(set (match_operand:SF 0 "gpc_reg_operand" "=r")
(unsigned_float:SF (match_operand:SI 1 "gpc_reg_operand" "r")))]
***************
*** 97,102 ****
--- 120,133 ----
"efscfui %0,%1"
[(set_attr "type" "fp")])
+ ;; FIXME fix expander.
+ (define_insn "spe_floatunssidf2"
+ [(set (match_operand:DF 0 "gpc_reg_operand" "=r")
+ (unsigned_float:DF (match_operand:SI 1 "gpc_reg_operand" "r")))]
+ "TARGET_HARD_FLOAT && TARGET_E500_DOUBLE"
+ "efdcfui %0,%1"
+ [(set_attr "type" "fp")])
+
(define_insn "spe_floatsisf2"
[(set (match_operand:SF 0 "gpc_reg_operand" "=r")
(float:SF (match_operand:SI 1 "gpc_reg_operand" "r")))]
***************
*** 104,109 ****
--- 135,147 ----
"efscfsi %0,%1"
[(set_attr "type" "fp")])
+ ;; FIXME: This isn't used right now. Fix the expander.
+ (define_insn "spe_floatsidf2"
+ [(set (match_operand:DF 0 "gpc_reg_operand" "=r")
+ (float:DF (match_operand:SI 1 "gpc_reg_operand" "r")))]
+ "TARGET_HARD_FLOAT && TARGET_E500_DOUBLE"
+ "efdcfsi %0,%1"
+ [(set_attr "type" "fp")])
;; SPE SIMD instructions
***************
*** 2147,2152 ****
--- 2185,2271 ----
[(set_attr "type" "vecstore")
(set_attr "length" "4")])
+ ;; Double-precision floating point instructions.
+ (define_insn "*movdf_e500_double"
+ [(set (match_operand:DF 0 "nonimmediate_operand" "=r,r,m,r,r,r")
+ (match_operand:DF 1 "input_operand" "r,m,r,G,H,F"))]
+ "TARGET_HARD_FLOAT && TARGET_E500_DOUBLE
+ && (gpc_reg_operand (operands[0], DFmode)
+ || gpc_reg_operand (operands[1], DFmode))"
+ "*
+ {
+ switch (which_alternative)
+ {
+ default:
+ abort ();
+ case 0:
+ return \"evor %0,%1,%1\";
+ case 1:
+ return \"evldd%X1 %0,%y1\";
+ case 2:
+ return \"evstdd%X0 %1,%y0\";
+ case 3:
+ case 4:
+ case 5:
+ abort (); /*fixme*/
+ return \"#\";
+ }
+ }"
+ [(set_attr "type" "*,vecload,vecstore,*,*,*")
+ (set_attr "length" "*,*,*,8,12,16")])
+
+ (define_insn "spe_truncdfsf2"
+ [(set (match_operand:SF 0 "gpc_reg_operand" "=r")
+ (float_truncate:SF (match_operand:DF 1 "gpc_reg_operand" "r")))]
+ "TARGET_HARD_FLOAT && TARGET_E500_DOUBLE"
+ "efscfd %0,%1")
+
+ (define_insn "spe_absdf2"
+ [(set (match_operand:DF 0 "gpc_reg_operand" "=r")
+ (abs:DF (match_operand:DF 1 "gpc_reg_operand" "r")))]
+ "TARGET_HARD_FLOAT && TARGET_E500_DOUBLE"
+ "efdabs %0,%1")
+
+ (define_insn "spe_nabsdf2"
+ [(set (match_operand:DF 0 "gpc_reg_operand" "=r")
+ (neg:DF (abs:DF (match_operand:DF 1 "gpc_reg_operand" "r"))))]
+ "TARGET_HARD_FLOAT && TARGET_E500_DOUBLE"
+ "efdnabs %0,%1")
+
+ (define_insn "spe_negdf2"
+ [(set (match_operand:DF 0 "gpc_reg_operand" "=r")
+ (neg:DF (match_operand:DF 1 "gpc_reg_operand" "r")))]
+ "TARGET_HARD_FLOAT && TARGET_E500_DOUBLE"
+ "efdneg %0,%1")
+
+ (define_insn "spe_adddf3"
+ [(set (match_operand:DF 0 "gpc_reg_operand" "=r")
+ (plus:DF (match_operand:DF 1 "gpc_reg_operand" "r")
+ (match_operand:DF 2 "gpc_reg_operand" "r")))]
+ "TARGET_HARD_FLOAT && TARGET_E500_DOUBLE"
+ "efdadd %0,%1,%2")
+
+ (define_insn "spe_subdf3"
+ [(set (match_operand:DF 0 "gpc_reg_operand" "=r")
+ (minus:DF (match_operand:DF 1 "gpc_reg_operand" "r")
+ (match_operand:DF 2 "gpc_reg_operand" "r")))]
+ "TARGET_HARD_FLOAT && TARGET_E500_DOUBLE"
+ "efdsub %0,%1,%2")
+
+ (define_insn "spe_muldf3"
+ [(set (match_operand:DF 0 "gpc_reg_operand" "=r")
+ (mult:DF (match_operand:DF 1 "gpc_reg_operand" "r")
+ (match_operand:DF 2 "gpc_reg_operand" "r")))]
+ "TARGET_HARD_FLOAT && TARGET_E500_DOUBLE"
+ "efdmul %0,%1,%2")
+
+ (define_insn "spe_divdf3"
+ [(set (match_operand:DF 0 "gpc_reg_operand" "=r")
+ (div:DF (match_operand:DF 1 "gpc_reg_operand" "r")
+ (match_operand:DF 2 "gpc_reg_operand" "r")))]
+ "TARGET_HARD_FLOAT && TARGET_E500_DOUBLE"
+ "efddiv %0,%1,%2")
+
;; Vector move instructions.
(define_expand "movv2si"
***************
*** 2549,2552 ****
--- 2668,2733 ----
1005))]
"TARGET_HARD_FLOAT && !TARGET_FPRS && flag_unsafe_math_optimizations"
"efststlt %0,%1,%2"
+ [(set_attr "type" "veccmpsimple")])
+
+ ;; Same thing, but for double-precision.
+
+ (define_insn "cmpdfeq_gpr"
+ [(set (match_operand:CCFP 0 "cc_reg_operand" "=y")
+ (unspec:CCFP
+ [(compare:CCFP (match_operand:DF 1 "gpc_reg_operand" "r")
+ (match_operand:DF 2 "gpc_reg_operand" "r"))]
+ 1006))]
+ "TARGET_HARD_FLOAT && TARGET_E500_DOUBLE && !flag_unsafe_math_optimizations"
+ "efdcmpeq %0,%1,%2"
+ [(set_attr "type" "veccmp")])
+
+ (define_insn "tstdfeq_gpr"
+ [(set (match_operand:CCFP 0 "cc_reg_operand" "=y")
+ (unspec:CCFP
+ [(compare:CCFP (match_operand:DF 1 "gpc_reg_operand" "r")
+ (match_operand:DF 2 "gpc_reg_operand" "r"))]
+ 1007))]
+ "TARGET_HARD_FLOAT && TARGET_E500_DOUBLE && flag_unsafe_math_optimizations"
+ "efdtsteq %0,%1,%2"
+ [(set_attr "type" "veccmpsimple")])
+
+ (define_insn "cmpdfgt_gpr"
+ [(set (match_operand:CCFP 0 "cc_reg_operand" "=y")
+ (unspec:CCFP
+ [(compare:CCFP (match_operand:DF 1 "gpc_reg_operand" "r")
+ (match_operand:DF 2 "gpc_reg_operand" "r"))]
+ 1008))]
+ "TARGET_HARD_FLOAT && TARGET_E500_DOUBLE && !flag_unsafe_math_optimizations"
+ "efdcmpgt %0,%1,%2"
+ [(set_attr "type" "veccmp")])
+
+ (define_insn "tstdfgt_gpr"
+ [(set (match_operand:CCFP 0 "cc_reg_operand" "=y")
+ (unspec:CCFP
+ [(compare:CCFP (match_operand:DF 1 "gpc_reg_operand" "r")
+ (match_operand:DF 2 "gpc_reg_operand" "r"))]
+ 1009))]
+ "TARGET_HARD_FLOAT && TARGET_E500_DOUBLE && flag_unsafe_math_optimizations"
+ "efdtstgt %0,%1,%2"
+ [(set_attr "type" "veccmpsimple")])
+
+ (define_insn "cmpdflt_gpr"
+ [(set (match_operand:CCFP 0 "cc_reg_operand" "=y")
+ (unspec:CCFP
+ [(compare:CCFP (match_operand:DF 1 "gpc_reg_operand" "r")
+ (match_operand:DF 2 "gpc_reg_operand" "r"))]
+ 1010))]
+ "TARGET_HARD_FLOAT && TARGET_E500_DOUBLE && !flag_unsafe_math_optimizations"
+ "efdcmplt %0,%1,%2"
+ [(set_attr "type" "veccmp")])
+
+ (define_insn "tstdflt_gpr"
+ [(set (match_operand:CCFP 0 "cc_reg_operand" "=y")
+ (unspec:CCFP
+ [(compare:CCFP (match_operand:DF 1 "gpc_reg_operand" "r")
+ (match_operand:DF 2 "gpc_reg_operand" "r"))]
+ 1011))]
+ "TARGET_HARD_FLOAT && TARGET_E500_DOUBLE && flag_unsafe_math_optimizations"
+ "efdtstlt %0,%1,%2"
[(set_attr "type" "veccmpsimple")])