This is the mail archive of the gcc@gcc.gnu.org mailing list for the GCC project.


Index Nav: [Date Index] [Subject Index] [Author Index] [Thread Index]
Message Nav: [Date Prev] [Date Next] [Thread Prev] [Thread Next]
Other format: [Raw text]

Re: More on memory barriers


On Wed, Sep 15, 2004 at 05:28:27PM -0400, Jason Merrill wrote:
> On the Alpha the problem has to do with its wacky cache-coherence rules,
> but on other architectures the problem has everything to do with
> speculation.  If the memory model allows the processor to execute loads out
> of order, you can run into the same problem by loading the contents of the
> guarded object before the flag.

For ppc this is only true if you use lwsync, correct?  
Using sync will kill speculation on other processors, correct?

For i386 and ia64, speculation is canceled by cache probes.


r~


Index Nav: [Date Index] [Subject Index] [Author Index] [Thread Index]
Message Nav: [Date Prev] [Date Next] [Thread Prev] [Thread Next]