Re: RFC: Using mode and code macros in *.md files

[Steve Ellcey <sje at cup dot hp dot com>]

I have a question about the mode macros.

On IA64, extending a floating point operand in a register is a noop so
it would be useful to fold that into actual floating point operations.

So if I had something like:

  ;; AF == Any floating point type that can fit in a register.
  (define_mode_macro AF [(SF "") (DF "") (XF "")])

  (define_insn "*addxf3_extend"
    [(set (match_operand:XF 0 "fr_register_operand" "=f")
          (plus:XF (float_extend:XF
                     (match_operand:AF 1 "fr_register_operand" "%f"))
                   (float_extend:XF
                     (match_operand:AF 2 "fr_reg_or_fp01_operand" "fG"))))]
    ""
    "fadd %0 = %1, %F2"
    [(set_attr "itanium_class" "fmac")])

Am I right in assuming that this would allow two SF operands, two DF
operands or two XF operands but would not allow, say, one SF operand and
one DF operand?

Could I work around that by defining AF1 and AF2 with the same
definition as AF and then using AF1 and AF2 in the instruction instead
of using AF twice?

It would be nice if I could fold the version of addxf3 that has no
float_extend's into this definition too but I don't think any macros or
existing mechanism would allow me to do that.

Steve Ellcey
sje@cup.hp.com