Re: cr logical instruction for powerpc target

[Geoff Keating <geoffk at geoffk dot org>]

On Aug 11, 2004, at 7:45 AM, David Edelsohn wrote:

> Gabriel Paubert writes:
>
> Gabriel> ;; Same as above, but get the GT bit.
> Gabriel> (define_insn "move_from_CR_eq_bit"
> Gabriel> [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
> Gabriel> (unspec:SI [(match_operand 1 "cc_reg_operand" "y")] 
> UNSPEC_MV_CR_EQ))]
> Gabriel> "TARGET_E500"
> Gabriel> "mfcr %0\;{rlinm|rlwinm} %0,%0,%D1,1"
> Gabriel> [(set_attr "type" "mfcr")
> Gabriel> (set_attr "length" "12")])
> Gabriel> ^^

> 	I think the "12" on that pattern and others is a left-over from
> Geoff's emit_sCOND change in early May 2003 removing an extra cror
> instruction generated for SCC instructions.  The extra bit twiddling 
> now
> should be explicit.
>
> 	I think it can be changed to "8", but maybe Geoff had a reason for
> leaving it "12".

No, it should be 8.

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